See veebileht kasutab küpsiseid kasutaja sessiooni andmete hoidmiseks. Veebilehe kasutamisega nõustute ETISe kasutustingimustega. Loe rohkem
Olen nõus

Aleksander Sudnitsõn

https://www.etis.ee/CV/Aleksander_Sudnitsõn/est
14.06.1950
6202255
5092356
aleksander.sudnitson@ttu.ee
http://ati.ttu.ee/~alsu/

Teenistuskäik

Töökohad ja ametid
01.09.2018–...   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, Dotsent (0,50)
01.01.2017–31.08.2018   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, Dotsent (1,00)
01.09.2008–31.12.2016   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Dotsent (1,00)
01.03.2007–31.08.2008   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Vanemteadur (0,50)
2007–2008   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Dotsent (0,50)
1995–2007   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Dotsent (1,00)
1992–1995   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Vanemteadur (1,00)
1987–1992   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Dotsent (1,00)
01.01.1987–31.12.1988   
Helsinki Tehnikaülikool; Külaline teadur
1983–1987   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Vanemõpetaja (1,00)
1978–1983   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Vaneminsener (1,00)
 
 
Haridustee
1978–1982   
Valgevene TA Küberneetika Instituut, aspirantuur
1967–1972   
Tallinna Tehnikaülikool, elektriinsener
 
 
Lisainfo
Õppetöö ainetes:
IAY0600 - Digitaalsüsteemide disain (Inglisekeelne magistriõppe kursus)
IAY0010 - Diskreetne matemaatika
IXX1430-Arvutisüsteemid - projekt
IXX1420 - Arvutid ja süsteemid - projekt
IXX9612 - Doktorantide õpetamispraktika

Kvalifikatsioon

Teaduskraadid
Aleksander Sudnitsõn, doktorikraad, 1984, (juh) Andres Keevallik; Arkadi Zakrevski, A Decomposition Method for PLD Synthesis, ETA Küberneetika Instituut, Tallinn.
 
 
Teadustöö põhisuunad
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.6. Arvutiteadused
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.6. Arvutiteadused
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.8. Elektrotehnika ja elektroonika; TÄPSUSTUS: Digitaal süsteemide süntees
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.8. Elektrotehnika ja elektroonika; TÄPSUSTUS: Asünkroonsite seadmete süntees
 
 
Lisainfo
tehnikateaduste kandidaat
1987, Küberneetika Instituut, Tallinn

Lõppenud projektid

Juhendamisel väitekirjad

Juhendatud väitekirjad

Publikatsioonid

Klass
Aasta
Publikatsioon
 
1.1.
2017
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2017). Fast Data Sort based on Searching Networks with Ring Pipeline. Elektronika ir Elektrotechnika, 23 (3), 74−77. DOI: 10.5755/j01.eie.22.4.15920.
1.1.
2017
Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A. (2017). Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems. Proceedings of the Estonian Academy of Sciences, 66 (3), 323−335.10.3176/proc.2017.3.07.
3.1.
2017
Rjabov, A.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2017). RAM-based mergers for data sort and frequent item computation. Proc. of 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO): 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), IEEE, Opatija, Croatia, May 22-26, 2017. IEEE, 176−181.10.23919/MIPRO.2017.7973413.
3.1.
2017
Skliarova, I.; Sklyarov, V.; Sudnitson, A.; Kruus, M. (2017). Reconfigurable Systems in Engineering Education: Best Practices and Future Trends. Proc. 2017 IEEE Global Engineering Education Conference (EDUCON): IEEE Global Engineering Education Conference (EDUCON), Athens, Greece, 25-28 April 2017. IEEE, 1084−1088.10.1109/EDUCON.2017.7942983.
1.1.
2016
Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A. (2016). Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems. International Journal of Computers Communications & Control, 11 (1), 126−141. DOI: 10.15837/ijccc.2016.1.1442.
1.1.
2016
Sklyarov, V.; Rjabov, A.; Skliarova, I.; Sudnitson, A. (2016). High-performance Information Processing in Distributed Computing Systems. International Journal of Innovative Computing, Information and Control, 12 (1), 139−160.
1.1.
2016
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2016). Fast Data Sort based on Searching Networks with Ring Pipeline. Elektronika ir Elektrotechnika, 22 (4), 58−62. DOI: 10.5755/j01.eie.22.4.15920.
3.1.
2016
Rjabov, A.; Sudnitson, A.; Sklyarov, V.; Skliarova, I. (2016). Interactions of Zynq-7000 devices with general purpose computers through PCI-express: A case study. 18th Mediterranean Electrotechnical Conference (MELECON), Lemesos, Cyprus, 18-20 April 2016. IEEE, 1−4.10.1109/MELCON.2016.7495400.
1.1.
2015
Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A. (2015). Zynq-based System for Extracting Sorted Subsets from Large Data Sets. Informacije MIDEM - Journal of Microelectronics Electronic Components and Materials, 45, 142−152.
1.1.
2015
Rjabov, A.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2015). Processing Sorted Subsets in a Multi-level Reconfigurable Computing System. Elektronika ir Elektrotechnika, 21 (2), 30−33.10.5755/j01.eee.21.2.11509.
3.1.
2015
Sklyarov, V.; Skliarova, I.; Silva, J.; Sudnitson, A.; Rjabov, A. (2015). Hardware Accelerators for Information Retrieval and Data Mining. 2015 International Conference on Information and Communication Technology Research (ICTRC), Abu Dhabi, United Arab Emirates, May 17-19, 2015. IEEE, 202−205.10.1109/ICTRC.2015.7156457.
3.1.
2015
Sklyarov, V.; Skliarova, I.; Sudnitson, A.; Kruus, M. (2015). FPGA-based Time and Cost Effective Hamming Weight Comparators for Binary Vectors. 16th International Conference on Computer as a Tool (IEEE EUROCON 2015), Salamanca, Spain, September 8-11, 2015. IEEE, 328−333.
3.1.
2015
Sklyarov, V.; Skliarova, I.; Silva, J.; Sudnitson, A. (2015). Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip. 18th Euromicro Conference on Digital Systems Design (DSD2015), Funchal, Madeira, Portugal, August 26-28, 2015. IEEE, 345−352. DOI: 10.1109/DSD.2015.45.
3.1.
2015
Sklyarov, V.; Skliarova, I.; Sudnitson, A.; Kruus, M. (2015). Integration of High-Level Synthesis to the Courses on Reconfigurable Digital Systems. 2015 38th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), Opatija, Croatia, May 25-29, 2015. IEEE, 166−171.10.1109/MIPRO.2015.7160258.
1.1.
2014
Skliarova, I.; Sklyarov, V.; Rjabov, A.; Sudnitson, A. (2014). Fast Matrix Covering in All Programmable Systems-on-Chip. Elektronika ir Elektrotechnika, 20 (5), 150−153.
1.2.
2014
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2014). FPGA-based Accelerators for Parallel Data Sort. Applied Computer Systems, 16, 53−63.
2.4.
2014
Sklyarov, V.; Skliarova, I.; Silva, J.; Rjabov, A.; Sudnitson, A.; Cardoso, C. (2014). Hardware/Software Co-design for Programmable Systems-on-Chip. TUT Press.
3.1.
2014
Sklyarov, V.; Skliarova, I.; Silva, J.; Sudnitson, A. (2014). Design Space Exploration in Multi-level Computing Systems. International Conference on Computer Systems and Technologies (CompSysTech 2014). ACM, 40−47. (ACM International Conference Proceeding Series; 883).
3.1.
2014
Skliarova, I.; Sklyarov, V.; Rjabov, A.; Sudnitson, A. (2014). Hardware/Software Co-design in Extensible Processing Platforms for Combinatorial Search Algorithms. 2014 17th IEEE Mediterranean Electrotechnical Conference (MELECON 2014), Beirut, Lebanon, Apr. 13-16, 2014. IEEE, 462−466.
3.1.
2014
Sklyarov, V.; Skliarova, I.; Silva, J.; Rjabov, A.; Sudnitson, A. (2014). Application of Extensible Processing Platforms for Experiments with FPGA-based Circuits. 2014 17th IEEE Mediterranean Electrotechnical Conference (MELECON 2014), Beirut, Lebanon, Apr. 13-16, 2014. IEEE, 467−471.
3.1.
2014
Skliarova, I.; Sklyarov, V.; Sudnitson, A.; Kruus, M. (2014). Teaching FPGA-based Systems. 2014 IEEE Global Engineering Education Conference (EDUCON), IEEE, Istanbul, Turkey, Apr. 2-5, 2014. IEEE, 460−469.
1.2.
2013
Skliarova, I.; Vallejo, T.; Sklyarov, V.; Sudnitson, A.; Kruus, M. (2013). Solving Computationally Intensive Problems in Reconfigurable Hardware:A Case Study. JCIT: Journal of Convergence Information Technology, 8 (3), 601−609.
3.1.
2013
Mihhailov, D.; Rjabov, A.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2013). Optimization of Address-based Data Sorting Unit with External Memory Support. International Conference on Computer Systems and Technologies (CompSysTech 2013): International Conference on Computer Systems and Technologies (CompSysTech 2013), Ruse Bulgaria, June 28-29, 2013. ACM, 83−90. (ACM International Conference Proceeding Series ; 767).
3.1.
2013
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2013). Processing N-ary Trees in Reconfigurable Hardware. Proc. 25th International Conference on Microelectronics (IEEE ICM 2013), IEEE, Beirut, Lebanon, Dec. 15-28, 2013: 25th International Conference on Microelectronics (IEEE ICM 2013), IEEE, Beirut, Lebanon, Dec. 15-28, 2013. IEEE, 13−16.
3.1.
2013
Sklyarov, V.; Skliarova, I.; Kruus, M.; Sudnitson, A. (2013). Using Mobile Technology to Enhance Teaching Reconfigurable Systems. Proc. IEEE International Conference on Teaching, Assessment and Learning for Engineering 2013 (IEEE TALE 2013), IEEE, Kuta, Indonesia, August 26-29, 2013. IEEE, 478−483.
3.1.
2013
Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A. (2013). Implementation of Parallel Operations over Streams in Extensible Processing Platforms. The 56th IEEE International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2013), Columbus, Ohio, USA, August 4-7, 2013. IEEE, 852−855.
3.1.
2013
Sklyarov, V.; Skliarova, I.; Kruus, M.; Mihhailov, D.; Sudnitson, A. (2013). Address-based Data Processing over N-ary Trees. IEEE EUROCON 2013, Zagreb, Croatia, July 1-4, 2013. IEEE, 1790−1797.
2.2.
2012
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2012). Design of FPGA-based Circuits using Hierarchical Finite State Machines. TTU Press.
3.1.
2012
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2012). Methodology and International Collaboration in Teaching Reconfigurable Systems. The 2012 IEEE Global Engineering Education Conference (IEEE EDUCON 2012), Marrakesh, Morocco, Apr. 17-20, 2012. IEEE, 1143−1152.
3.1.
2012
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2012). Implementation of Sorting Algorithms in Reconfigurable Hardware. The 2012 IEEE Mediterranean Electrotechnical Conference (MELECON 2012), Hammamet, Tunisia, March 25-28, 2012. IEEE, 107−110.
3.1.
2012
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2012). Performance Evaluation for FPGA-based Processing of Tree-Like Structures. 19 th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS), Seville, Spain, Dec. 9-12, 2012. IEEE, 217−220.
3.1.
2012
Mihhailov, D.; Sudnitson, A.; Sklyarov, V.; Skliarova, I. (2012). Implementation of Address-Based Data Sorting on Different FPGA Platforms. Proc. of 10th East-West Design & Test Symposium (EWDTS’2012), Kharkov, Ukraine, September 14-17, 2012. IEEE, 38−41.
1.1.
2011
Sagahyroon, F.; Aloul, A.; Sudnitson, A. (2011). Using SAT-Based Techniques in Low Power State Assignment. Journal of Circuits Systems and Computers, 20 (8), 1605−1618.10.1142/S0218126611007980.
1.1.
2011
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). Acceleration of Recursive Data Sorting over Tree-based Structures. Electronics and Electrical Engineering, 51−56.
3.1.
2011
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). Hardware Implementation of Recursive Sorting Algorithms. The 2011 International Conference on Electronic Devices, Systems & Applications (ICEDSA 2011), IEEE, Kuala Lumpur, Malaysia, April 25-27, 2011. IEEE, 33−38.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). High-performance Hardware Accelerators for Sorting and Managing Priorities. IEEE Symposium of Design and Diagnostics of Electronic Circuits and Systems ( DDECS 2011), Cottbus, Germany, April 13-15, 2011. IEEE, 313−318.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Oliveira, R.; Mihhailov, D.; Sudnitson, A. (2011). Processing Tree-like Data Structures in Different Computing Platforms. 2011 International Conference on Information and Computer Applications (ICICA 2011), Dubai, United Arab Emirates, March. 18-20, 2011. IEEE, 112−116.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). Processing Tree-like Data Structures for Sorting and Managing Priorities. Proc. the 2011 IEEE Symposium on Computer and Informatics: The 2011 IEEE Symposium on Computer and Informatics (ISCI 2011). Kuala Lumpur, Malaysia: IEEE, 322−327.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). Multilevel Models for Data Processing. Proc. the 2011 IEEE GCC Conference and Exhibition (2011 IEEE GCC): The 2011 IEEE GCC Conference and Exhibition (2011 IEEE GCC), Dubai, United Arab Emirates, Feb. 19-22, 2011. IEEE, 136−139.
3.1.
2011
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). Optimization of Recursive Sorting Algorithms for Implementation in Hardware. ICM'10: 2010 International Conference on Microelectronics: 22nd International Conference on Microelectronics (ICM 2010), Cairo, Egypt, Dec. 19-22, 2010. IEEE Electron Devices Society, 471−474.10.1109/ICM.2010.5696191.
3.1.
2011
Mihhailov, D.; Sklyarov, V.; Skliarova, J.; Sudnitson, A. (2011). Application-specific hardware accelerator for implementing recursive sorting algorithms. The 2010 International Conference on Field-Programmable Technology (FPT'10), Beijing, China, Dec. 8-10, 2010. IEEE, 269−272.10.1109/FPT.2010.5681486.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). FPGA-based Systems in Information and Communication. The 5th International Conference on Application of Information and Communication Technologies (AICT2011), Baku, Azerbaijan, Oct. 12-14, 2011. IEEE, 551−555.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). Implementation in FPGA of Address-based Data Sorting. The 21st International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Crete, Greece, Sep. 5-7, 2011. IEEE Computer Society, 405−410.
3.1.
2011
Mihhailov, D.; Kruus, M.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). Recursion and Hierarchy in Digital Design and Prototyping: A Case Study. International Conference on Computer Systems and Technologies (CompSysTech’2011),Vienna, Austria, 16-17 June 2011. NY, USA: ACM, 45−50. ( ACM International Conference Proceeding Series; 578).
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). Processing N-ary Trees in Hardware Circuits. 2011 International Symposium on Integrated Circuits (ISIC 2011), Singapore, Dec. 12-14. IEEE, 272−275.
1.1.
2010
Sudnitson, Alexander; Mihhailov, Dmitri; Kruus, Margus (2010). Project-Oriented Approach to Low-Power Topics in Advanced Digital Design Course. Electronics and Electrical Engineering, 151−154.
3.1.
2010
Sagahyroon, F.; Aloul, A.; Sudnitson, A. (2010). Low Power State Assignment Using ILP Techniques. The 15th IEEE Mediterranean Electrotechnical Conference – MELCON-2010. Valletta, Malta, April 25-28, 2010. IEEE, 850−855.
3.1.
2010
Mihhailov, D.; Sudnitson, A.; Tarletski, K. (2010). Web-Based Tool for FSM Encoding Targeting Low-Power FPGA Implementation. The 27th International Conference on Microelectronics– MIEL-2010. Nis, Serbia, May 16-19, 2010. IEEE, 349−352.
3.1.
2010
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2010). Parallel FPGA-based Implementation of Recursive Sorting Algorithms. The 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010), Cancun, Mexico, Dec. 13-15, 2010. IEEE Computer Society Press, 121−126.10.1109/ReConFig.2010.30.
3.1.
2010
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2010). Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules. Proceedings : 2010 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, 13–15 December 2010. Ed. Viktor Prasanna, Juergen Becker, and René Cumplido. IEEE Computer Society Press, 436−441.10.1109/ReConFig.2010.29.
3.1.
2010
Mihhailov, D.; Sklyarov, V.; Skliarova, J.; Sudnitson, A. (2010). Optimization of FPGA-based Circuits for Recursive Data Sorting. BEC 2010 : 12th biennial Baltic Electronics Conference : proceedings of the 12th biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia. Tallinn: IEEE, 129−132.
3.1.
2010
Mihhailov, Dmitri; Sklyarov, Valery; Skliarova, Iouliia; Sudnitson, Alexander (2010). Hardware Implementation of Recursive Algorithms. 53rd IEEE International Midwest Symposium on Circuits and Systems - IEEE MWSCAS 2010, Seattle, WA, USA, August 1-4, 2010. IEEE, 225−228.
3.1.
2009
Sudnitson, Alexander; Mihhailov, Dmitri; Kruus, Margus (2009). Cooperation of FPGA-Based Educational Boards and Web-Based Point Design Tools for Research and Education. IFIP EduTech’09International Workshop, Florianopolis- Brazil, Oct.15-16.
3.1.
2009
Sudnitson, A.; Mihhailov, D.; Kruus, M.; Tarletski, K. (2009). FSM Decomposition with Application to FPGA Synthesis. Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing: International Conference on Computer Systems and Technologies-CompSysTech’09, Ruse, Bulgaria. Ed. B. Rachev, A. Smrikarov. ACM, IV.4.1−IV.4.6. (ACM International Conference Proceeding Series; 433).
3.1.
2009
Sudnitson, Alexander; Mihhailov, Dimitri; Kruus, Margus (2009). Advanced Topics of FSM Design Using FPGA Educational Boards and Web-Based Tools. IEEE East-West Design & Test Symposium, Moscow, Russia. 446−449.
3.1.
2008
Mihhailov, D.; Kruus, M.; Sudnitson, A. (2008). FPGA Platform Based Digital Design Education. Proceedings of the 9th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing: International Conference on Computer Systems and Technologies (CompSysTech’2008), Gabrovo, Bulgaaria. Ed. B. Rachev, A. Smrikarov. ACM, IV.1−IV.6. (ACM International Conference Proceeding Series; 374).
3.1.
2008
Devadze, Sergei (2008). Software Environment for Synthesis of Testable FSM through Decomposition. IEEE 26th International Conference on Microelectronics (MIEL 2008), Nis, Serbia. 433−436.
3.1.
2008
Ellervee, P.; Reinsalu, U.; Arhipov, A.; Ivask, E.; Tammemäe, K.; Evartson, T.; Sudnitson, A. (2008). HDL-s and FPGA-s in Digital Design Education. The 19th EAEEIE Annual Conference, Tallinn, Estonia, June 2008. 37−41.
3.1.
2007
Sudnitson, Alexander; Devadze, Sergei (2007). Web-Based Computer Aided Design Support of Finite State Machine Additive Decomposition for Low Power. 5th IEEE East-West Design & Test International Symposium. 494−498.
3.2.
2007
Sudnitsõn, A. (2007). Computer Engineering. In: PhD in Computer Science, Computer Engineering, Software Engineering, Information Systems (121−192).. European Thematic Network 114046-CP-1-BG-ERASMUS-TN. Publishing Company at the University of Rousse..
3.2.
2006
Wuttke, H.-D.; Sudnitson, A.; Henke, K (2006). E-Learning Tools for Teaching the Design and Validation of "Finite State Machines"". In: E-Learning and the Knowledge Society (327−341).. Gent, Belgia: Communication and Cognition .
3.4.
2006
Sudnitson, Alexander; Kruus, Margus (2006). E-Learning Tools for Teaching the Decomposition Based Digital Synthesis. EWME 2006 Proceedings (6-th European Workshop on Microelectronics Education), Stockholm, Sweden, 2006. Stockholm, Sweden: Royal Institue of Technology KTH, 63−66.
3.4.
2006
Smrikarov, A.; Smrikarova, S.; Kruus, M.; Sudnitson, A. (2006). European Thematic Network for Doctoral Education in Computing. Annex of Advances in Current Natural Sciences, Moscow: Academy of Natural Sciences: 33d International Conference on Information Technologies in Science, Education, Telecommunication, Business (IT+SE’2006), Gurzuf, Ukraine. 339−340.
3.4.
2006
Sudnitson, Alexander; Sergei, Devadze (2006). Computer Aided Design Support of FSM Multiplicative Decomposition. IEEE East-West Design&Test International Workshop (EWDTW'06), Sochi, Russia. 241−246.
3.1.
2005
"Devadze, Sergei;Sudnitsõn, Aleksander" (2005). FSM decomposition software for education and research. Proc. IEEE EUROCON 2005 International Conference on Computer as a tool : Belgrade, Serbia & Montenegro. Belgrad: TTY puuduv kirjastus, 839−842.
3.2.
2005
Sudnitsõn, Aleksander (2005). Research and training environment for decomposition-based logical design. In: COMMUNICATION&COGNITION (3.12.1−3.12.7).. Ghent: TTY puuduv kirjastus.
3.4.
2005
Jutman, A.; Rosin, V.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2005). A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard. Proc. of 16th EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering: Lappeenranta, Finland, June 6-8, 2005.
3.4.
2005
Jutman, A.; Kruus, M.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2005). Web-Based Software Package for e-Learning and Research Training in Digital System design. Proc. 32nd International Conference on Information Technologies in Science, Education, Telecommunication, Business: IT+SE'2005, Gurzuf, Ukraine. 306−308.
3.4.
2005
"Fomina, Jelena;Sudnitsõn, Aleksander" (2005). Extended finite state machine decomposition for low power. Proceedings 19th International Conference on Systems for Automation of Engineering and Research : SAER'2005 : Varna, Bulgaria, 2005. Varna, 126−131.
1.2.
2004
Kruus, M.; Lensen, H.; Sudnitson, A. (2004). Digital Design at Microarchtectural Level Based on Quality Relationship Measures. Advances in Current Natural Sciences, 5, 1, 29−31.
3.1.
2004
Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2004). E-Learning Environment in the Area of Digital Microelectronics. Proc. of Int. Conf. on Information Technology Based Higher Education and Training: ITHET’04, Istanbul, Turkey, May 31 – June 2, 2004. IEEE, 278−283.
3.1.
2004
"Fomina, Jelena;Sudnitsõn, Aleksander;Vasiliev, Roman" (2004). Optimization of FSMs network by new encoding strategy. BEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia. Tallinn: Tallinn University of Technology, 119−122.
3.1.
2004
Sudnitson, A. (2004). Register transfer low power design based on controller decomposition. 2: 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716). Piscataway, NJ, USA. 735−738. (IEEE; 04TH8716).
3.4.
2004
"Fomina, Jelena;Sudnitsõn, Aleksander" (2004). Information relationships for decomposition of finite state machine. East-West Design & Test Workshop. 41−47.
3.4.
2004
"Fomina, Jelena;Sudnitsõn, Aleksander;Vasiliev, Roman" (2004). FSM's network encoding guided by information relationship measure. 6th International Workshop on Boolean Problems. Freiberg, Germany: TTY puuduv kirjastus, 55−62.
3.4.
2004
Fomina, E.; Ellervee, P.; Kruus, M.; Sudnitson, A; Tammemae, K. (2004). Digital synthesis tools for education and research. The 18th International Conference on Systems for Automation of Engineering and Research (SAER'2004), Varna, Bulgaria, 2004.. 160−164.
3.4.
2004
Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2004). Asynchronous E-Leaning Resources for Hardware Design Issues. Proc. of the International Conference on Computer Systems and Technologies: CompSysTech'2004, Sofia, Bulgaria, 2004. 1−6.
3.1.
2003
Devadze, Sergei; Fomina, Jelena; Kruus, Margus; Sudnitsõn, Aleksander (2003). Web-based system for sequential machines decomposition. In: EUROCON 2003. Computer as a Tool. (57−61).. [S. l.]: IEEE.
3.1.
2003
Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2003). Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test. Proc. of 4th International Conference on Information Technology Based Higher Education and Training: ITHET'03, Marrakech, Morocco, July 7-9, 2003. 397−401.
3.1.
2003
Fomina, E.; Keevallik, A.; Kruus, M.; Sudnitson, A. (2003). A decomposition procedure for register-transfer level power management. Proceedings of the International Conference on Computer Systems and Technologies (e-Learning) (1.2−1.6).. Sofia: Bulgarian Academy of Science.
3.4.
2003
Jutman, A.; Sudnitson, A.; Ubar, R. (2003). Web-Based Training System for Teaching Principles of Boundary Scan Technique. Proc. 14th EAEEIE Conference on Innovation in Education for Electrical and Information Engineering: Gdansk, Poland, June 16-18, 2003.
3.4.
2003
Jutman, A.; Sudnitson, A.; Ubar, R. (2003). Digital Design Learning System Based on Java Applets. Proc. 4th Annual Conference of the LTSN Centre for Information and Computer Sciences: NUI Galway, Ireland, August 26-28, 2003. 183−187.
3.4.
2003
Jutman, A.; Sudnitson, A.; Ubar, R. (2003). Web-based Applet for Teaching Boundary Scan Standard IEEE 1149.1. Proc. of 10th International Conference on Mixed Design of Integrated Circuits and Systems: MIXDES'03, Lodz, Poland, June 26-28, 2003. 584−589.
3.4.
2003
"Sudnitsõn, Aleksander;Jamšanov, A." (2003). A FSM decomposition method for mixed synchronous/asynchronous implementation. Proc. 17th International Conference on Systems for Automation of Engineering and Research : SAER'2003 : Varna, Bulgaria, 2003. 37−41.
3.1.
2002
Fomina, E.; Keevallik, A.; Kruus, A.; Sudnitson, A. (2002). Web-based tools for finite state machine decomposition with analysis of information flows. BEC 2002. Proceedings of the 8th Biennial Baltic Electronics Conference: 8th Biennial Baltic Electronics Conference. Tallinn: Tallinn Technical University, 165−168.
3.1.
2002
Sudnitson, A. (2002). Computational kernel extraction for synthesis of power-managed sequential components. 2: ICECS 2002. 9th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.02EX611). Piscataway, NJ, USA. IEEE, 749−752.
3.1.
2002
Sudnitson, A. (2002). An approach to synthesis of mixed synchronous/asynchronous digital devices. 2: 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595). Piscataway, NJ, USA. IEEE, 695−698.
3.1.
2002
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2002). Java Technology Based Training System for Teaching Digital Design and Test. Proc. of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002: 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002. 283−286.
3.1.
2002
Fomina, E.; Keevallik, A.; Sudnitson, A (2002). Low power synthesis based on information theoretic measures. 23rd International Conference on Microelectronics. Proceedings, 2: 23rd International Conference on Microelectronics. Piscataway, NJ, USA: IEEE, 699−702.
3.2.
2002
Kruus, Margus; Lensen, Harri; Sudnitsõn, Aleksander (2002). Web-based tools for decomposition-oriented digital design. 1: MEET/MARIND'2002 : proceedings of First International Congress on Mechanical and Electrical Engineering and Technology and Fourth International Conference on Marine Industry, 07-11 October 2002, Varna Bulgaria. Varna: TTY puuduv kirjastus, 261−266.
3.4.
2002
Devadze, S.; Jutman, A.; Kruus, M.; Sudnitson, A.; Ubar, R. (2002). Web Based Tools for Synthesis and Testing of Digital Devices. Proc. International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002: International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002. I.91−I.96.
3.4.
2002
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R. (2002). Web-based training system for teaching basics of RT-level Digital Design, Test, and Design for Test. Proc. of 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002: 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002. 699−704.
3.4.
2002
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2002). Teaching Digital RT-Level Self-Test using a Java Applet. 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002. 322−328.
3.4.
2002
"Fomina, Jelena;Keevallik, Andres;Sudnitsõn, Aleksander" (2002). Entropic analysis of finite state mashines' networks. IEEE 5th International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2002). Brno: Brno University of Technology, 244−251.
3.4.
2002
Sudnitsõn, Aleksander (2002). Integrating dynamic power management in the register transfer level synthesis. 1: MEET/MARIND'2002 : proceedings of First International Congress on Mechanical and Electrical Engineering and Technology and Fourth International Conference on Marine Industry, 07-11 October 2002, Varna Bulgaria. Varna, 267−274.
3.2.
2001
Devadze, Sergei; Kruus, Margus; Sudnitsõn, Aleksander (2001). Web-based software implementation of finite state machine decomposition for design and education. Proc. International Conference on Computer Systems and Technologies : CompSys'2001 : Sofia, Bulgaria, 2001.
3.4.
2001
Sudnitsõn, Aleksander (2001). Finite state machines with datapath partitioning for low power synthesis. Proceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 2000. [S. l.], 163−168.
3.4.
2001
Sudnitsõn, Aleksander (2001). Functional partitioning for register transfer level low power synthesis. ECS'01 : proceedings of the 3rd Electronic Circuits and Systems Conference : September 5-7, 2001, Bratislava, Slovakia. [S. l.], 73−76.
3.4.
2001
Kruus, M.; Lensen, H.; Sudnitsõn, A. (2001). Synthesis of Sequential Circuits with Dynamic Power Management. Proceedings of RTUCET '01, Oct. 12, 2001, Riga.
3.4.
2000
"Sudnitsõn, Aleksander;Levenko, Aleksei;Andreev, Dmitri" (2000). Java-based system for finite state machine decomposition. In: 45th International Scientific Colloquium IWK2000 (961−965).. Ilmenau, Germany: Technische Universität Ilmenau.
3.4.
2000
Sudnitsõn, Aleksander (2000). Partition search problem for finite state machine decomposition. 45th International Scientific Colloquium IWK2000. [Ilmenau]: Frank Cass, 673−678.
3.4.
2000
Sudnitsõn, Aleksander (2000). Finite state machine synthesis for low power using input-disabling precomputation architectures. "The 7th Biennial Conference on Electronics and Microsystem Technology ""Baltic Electronics Conference"" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings". [Tallinn]: Tallinn Technical University, 137−140.
29.04.2019

Aleksander Sudnitsõn

https://www.etis.ee/CV/Aleksander_Sudnitsõn/eng
14.06.1950
6202255
5092356
aleksander.sudnitson@ttu.ee

Career

Institutions and positions
01.09.2018–...   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Associate Professor (0,50)
01.01.2017–31.08.2018   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Associate Professor (1,00)
01.09.2008–31.12.2016   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Associate Professor (1,00)
01.03.2007–31.08.2008   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Senior Researcher (0,50)
2007–2008   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Associate Professor (0,50)
1995–2007   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Associate Professor (1,00)
1992–1995   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Senior Researcher (1,00)
1987–1992   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Associate Professor (1,00)
01.01.1987–31.12.1988   
Helsinki University of Technology; Guest Reseacher
1983–1987   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Senior Teacher (1,00)
1978–1983   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Senior Engineer (1,00)
 
 
Education
1978–1982   
Byelorussian Institute of Cybernetics, PhD study
1967–1972   
Tallinn University of Technology, Electrical Engineering
 
 
Additional information
Õppetöö ainetes:
IAY0600 - Digitaalsüsteemide disain (Inglisekeelne magistriõppe kursus)
IAY0010 - Diskreetne matemaatika
IXX1430-Arvutisüsteemid - projekt
IXX1420 - Arvutid ja süsteemid - projekt
IXX9612 - Doktorantide õpetamispraktika

Qualifications

Academic degrees
Aleksander Sudnitsõn, Doctor's Degree, 1984, (sup) Andres Keevallik; Arkadi Zakrevski, A Decomposition Method for PLD Synthesis, Estonian Academy of Sciences, Institute of Cybernetiks, Tallinn.
 
 
Fields of research
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.6. Computer Sciences
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.6. Computer Sciences
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.8. Electrical Engineering and Electronics
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.8. Electrical Engineering and Electronics
 
 
Additional information
Ph.D.
1984, Institute of Cybernetics, Tallinn

Completed projects

Dissertations under supervision

Supervised dissertations

Publications

Category
Year
Publication
 
1.1.
2017
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2017). Fast Data Sort based on Searching Networks with Ring Pipeline. Elektronika ir Elektrotechnika, 23 (3), 74−77. DOI: 10.5755/j01.eie.22.4.15920.
1.1.
2017
Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A. (2017). Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems. Proceedings of the Estonian Academy of Sciences, 66 (3), 323−335.10.3176/proc.2017.3.07.
3.1.
2017
Rjabov, A.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2017). RAM-based mergers for data sort and frequent item computation. Proc. of 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO): 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), IEEE, Opatija, Croatia, May 22-26, 2017. IEEE, 176−181.10.23919/MIPRO.2017.7973413.
3.1.
2017
Skliarova, I.; Sklyarov, V.; Sudnitson, A.; Kruus, M. (2017). Reconfigurable Systems in Engineering Education: Best Practices and Future Trends. Proc. 2017 IEEE Global Engineering Education Conference (EDUCON): IEEE Global Engineering Education Conference (EDUCON), Athens, Greece, 25-28 April 2017. IEEE, 1084−1088.10.1109/EDUCON.2017.7942983.
1.1.
2016
Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A. (2016). Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems. International Journal of Computers Communications & Control, 11 (1), 126−141. DOI: 10.15837/ijccc.2016.1.1442.
1.1.
2016
Sklyarov, V.; Rjabov, A.; Skliarova, I.; Sudnitson, A. (2016). High-performance Information Processing in Distributed Computing Systems. International Journal of Innovative Computing, Information and Control, 12 (1), 139−160.
1.1.
2016
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2016). Fast Data Sort based on Searching Networks with Ring Pipeline. Elektronika ir Elektrotechnika, 22 (4), 58−62. DOI: 10.5755/j01.eie.22.4.15920.
3.1.
2016
Rjabov, A.; Sudnitson, A.; Sklyarov, V.; Skliarova, I. (2016). Interactions of Zynq-7000 devices with general purpose computers through PCI-express: A case study. 18th Mediterranean Electrotechnical Conference (MELECON), Lemesos, Cyprus, 18-20 April 2016. IEEE, 1−4.10.1109/MELCON.2016.7495400.
1.1.
2015
Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A. (2015). Zynq-based System for Extracting Sorted Subsets from Large Data Sets. Informacije MIDEM - Journal of Microelectronics Electronic Components and Materials, 45, 142−152.
1.1.
2015
Rjabov, A.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2015). Processing Sorted Subsets in a Multi-level Reconfigurable Computing System. Elektronika ir Elektrotechnika, 21 (2), 30−33.10.5755/j01.eee.21.2.11509.
3.1.
2015
Sklyarov, V.; Skliarova, I.; Silva, J.; Sudnitson, A.; Rjabov, A. (2015). Hardware Accelerators for Information Retrieval and Data Mining. 2015 International Conference on Information and Communication Technology Research (ICTRC), Abu Dhabi, United Arab Emirates, May 17-19, 2015. IEEE, 202−205.10.1109/ICTRC.2015.7156457.
3.1.
2015
Sklyarov, V.; Skliarova, I.; Sudnitson, A.; Kruus, M. (2015). FPGA-based Time and Cost Effective Hamming Weight Comparators for Binary Vectors. 16th International Conference on Computer as a Tool (IEEE EUROCON 2015), Salamanca, Spain, September 8-11, 2015. IEEE, 328−333.
3.1.
2015
Sklyarov, V.; Skliarova, I.; Silva, J.; Sudnitson, A. (2015). Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip. 18th Euromicro Conference on Digital Systems Design (DSD2015), Funchal, Madeira, Portugal, August 26-28, 2015. IEEE, 345−352. DOI: 10.1109/DSD.2015.45.
3.1.
2015
Sklyarov, V.; Skliarova, I.; Sudnitson, A.; Kruus, M. (2015). Integration of High-Level Synthesis to the Courses on Reconfigurable Digital Systems. 2015 38th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), Opatija, Croatia, May 25-29, 2015. IEEE, 166−171.10.1109/MIPRO.2015.7160258.
1.1.
2014
Skliarova, I.; Sklyarov, V.; Rjabov, A.; Sudnitson, A. (2014). Fast Matrix Covering in All Programmable Systems-on-Chip. Elektronika ir Elektrotechnika, 20 (5), 150−153.
1.2.
2014
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2014). FPGA-based Accelerators for Parallel Data Sort. Applied Computer Systems, 16, 53−63.
2.4.
2014
Sklyarov, V.; Skliarova, I.; Silva, J.; Rjabov, A.; Sudnitson, A.; Cardoso, C. (2014). Hardware/Software Co-design for Programmable Systems-on-Chip. TUT Press.
3.1.
2014
Sklyarov, V.; Skliarova, I.; Silva, J.; Sudnitson, A. (2014). Design Space Exploration in Multi-level Computing Systems. International Conference on Computer Systems and Technologies (CompSysTech 2014). ACM, 40−47. (ACM International Conference Proceeding Series; 883).
3.1.
2014
Skliarova, I.; Sklyarov, V.; Rjabov, A.; Sudnitson, A. (2014). Hardware/Software Co-design in Extensible Processing Platforms for Combinatorial Search Algorithms. 2014 17th IEEE Mediterranean Electrotechnical Conference (MELECON 2014), Beirut, Lebanon, Apr. 13-16, 2014. IEEE, 462−466.
3.1.
2014
Sklyarov, V.; Skliarova, I.; Silva, J.; Rjabov, A.; Sudnitson, A. (2014). Application of Extensible Processing Platforms for Experiments with FPGA-based Circuits. 2014 17th IEEE Mediterranean Electrotechnical Conference (MELECON 2014), Beirut, Lebanon, Apr. 13-16, 2014. IEEE, 467−471.
3.1.
2014
Skliarova, I.; Sklyarov, V.; Sudnitson, A.; Kruus, M. (2014). Teaching FPGA-based Systems. 2014 IEEE Global Engineering Education Conference (EDUCON), IEEE, Istanbul, Turkey, Apr. 2-5, 2014. IEEE, 460−469.
1.2.
2013
Skliarova, I.; Vallejo, T.; Sklyarov, V.; Sudnitson, A.; Kruus, M. (2013). Solving Computationally Intensive Problems in Reconfigurable Hardware:A Case Study. JCIT: Journal of Convergence Information Technology, 8 (3), 601−609.
3.1.
2013
Mihhailov, D.; Rjabov, A.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2013). Optimization of Address-based Data Sorting Unit with External Memory Support. International Conference on Computer Systems and Technologies (CompSysTech 2013): International Conference on Computer Systems and Technologies (CompSysTech 2013), Ruse Bulgaria, June 28-29, 2013. ACM, 83−90. (ACM International Conference Proceeding Series ; 767).
3.1.
2013
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2013). Processing N-ary Trees in Reconfigurable Hardware. Proc. 25th International Conference on Microelectronics (IEEE ICM 2013), IEEE, Beirut, Lebanon, Dec. 15-28, 2013: 25th International Conference on Microelectronics (IEEE ICM 2013), IEEE, Beirut, Lebanon, Dec. 15-28, 2013. IEEE, 13−16.
3.1.
2013
Sklyarov, V.; Skliarova, I.; Kruus, M.; Sudnitson, A. (2013). Using Mobile Technology to Enhance Teaching Reconfigurable Systems. Proc. IEEE International Conference on Teaching, Assessment and Learning for Engineering 2013 (IEEE TALE 2013), IEEE, Kuta, Indonesia, August 26-29, 2013. IEEE, 478−483.
3.1.
2013
Sklyarov, V.; Skliarova, I.; Rjabov, A.; Sudnitson, A. (2013). Implementation of Parallel Operations over Streams in Extensible Processing Platforms. The 56th IEEE International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2013), Columbus, Ohio, USA, August 4-7, 2013. IEEE, 852−855.
3.1.
2013
Sklyarov, V.; Skliarova, I.; Kruus, M.; Mihhailov, D.; Sudnitson, A. (2013). Address-based Data Processing over N-ary Trees. IEEE EUROCON 2013, Zagreb, Croatia, July 1-4, 2013. IEEE, 1790−1797.
2.2.
2012
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2012). Design of FPGA-based Circuits using Hierarchical Finite State Machines. TTU Press.
3.1.
2012
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2012). Methodology and International Collaboration in Teaching Reconfigurable Systems. The 2012 IEEE Global Engineering Education Conference (IEEE EDUCON 2012), Marrakesh, Morocco, Apr. 17-20, 2012. IEEE, 1143−1152.
3.1.
2012
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2012). Implementation of Sorting Algorithms in Reconfigurable Hardware. The 2012 IEEE Mediterranean Electrotechnical Conference (MELECON 2012), Hammamet, Tunisia, March 25-28, 2012. IEEE, 107−110.
3.1.
2012
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2012). Performance Evaluation for FPGA-based Processing of Tree-Like Structures. 19 th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS), Seville, Spain, Dec. 9-12, 2012. IEEE, 217−220.
3.1.
2012
Mihhailov, D.; Sudnitson, A.; Sklyarov, V.; Skliarova, I. (2012). Implementation of Address-Based Data Sorting on Different FPGA Platforms. Proc. of 10th East-West Design & Test Symposium (EWDTS’2012), Kharkov, Ukraine, September 14-17, 2012. IEEE, 38−41.
1.1.
2011
Sagahyroon, F.; Aloul, A.; Sudnitson, A. (2011). Using SAT-Based Techniques in Low Power State Assignment. Journal of Circuits Systems and Computers, 20 (8), 1605−1618.10.1142/S0218126611007980.
1.1.
2011
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). Acceleration of Recursive Data Sorting over Tree-based Structures. Electronics and Electrical Engineering, 51−56.
3.1.
2011
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). Hardware Implementation of Recursive Sorting Algorithms. The 2011 International Conference on Electronic Devices, Systems & Applications (ICEDSA 2011), IEEE, Kuala Lumpur, Malaysia, April 25-27, 2011. IEEE, 33−38.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). High-performance Hardware Accelerators for Sorting and Managing Priorities. IEEE Symposium of Design and Diagnostics of Electronic Circuits and Systems ( DDECS 2011), Cottbus, Germany, April 13-15, 2011. IEEE, 313−318.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Oliveira, R.; Mihhailov, D.; Sudnitson, A. (2011). Processing Tree-like Data Structures in Different Computing Platforms. 2011 International Conference on Information and Computer Applications (ICICA 2011), Dubai, United Arab Emirates, March. 18-20, 2011. IEEE, 112−116.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). Processing Tree-like Data Structures for Sorting and Managing Priorities. Proc. the 2011 IEEE Symposium on Computer and Informatics: The 2011 IEEE Symposium on Computer and Informatics (ISCI 2011). Kuala Lumpur, Malaysia: IEEE, 322−327.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). Multilevel Models for Data Processing. Proc. the 2011 IEEE GCC Conference and Exhibition (2011 IEEE GCC): The 2011 IEEE GCC Conference and Exhibition (2011 IEEE GCC), Dubai, United Arab Emirates, Feb. 19-22, 2011. IEEE, 136−139.
3.1.
2011
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). Optimization of Recursive Sorting Algorithms for Implementation in Hardware. ICM'10: 2010 International Conference on Microelectronics: 22nd International Conference on Microelectronics (ICM 2010), Cairo, Egypt, Dec. 19-22, 2010. IEEE Electron Devices Society, 471−474.10.1109/ICM.2010.5696191.
3.1.
2011
Mihhailov, D.; Sklyarov, V.; Skliarova, J.; Sudnitson, A. (2011). Application-specific hardware accelerator for implementing recursive sorting algorithms. The 2010 International Conference on Field-Programmable Technology (FPT'10), Beijing, China, Dec. 8-10, 2010. IEEE, 269−272.10.1109/FPT.2010.5681486.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). FPGA-based Systems in Information and Communication. The 5th International Conference on Application of Information and Communication Technologies (AICT2011), Baku, Azerbaijan, Oct. 12-14, 2011. IEEE, 551−555.
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). Implementation in FPGA of Address-based Data Sorting. The 21st International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Crete, Greece, Sep. 5-7, 2011. IEEE Computer Society, 405−410.
3.1.
2011
Mihhailov, D.; Kruus, M.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2011). Recursion and Hierarchy in Digital Design and Prototyping: A Case Study. International Conference on Computer Systems and Technologies (CompSysTech’2011),Vienna, Austria, 16-17 June 2011. NY, USA: ACM, 45−50. ( ACM International Conference Proceeding Series; 578).
3.1.
2011
Sklyarov, V.; Skliarova, I.; Mihhailov, D.; Sudnitson, A. (2011). Processing N-ary Trees in Hardware Circuits. 2011 International Symposium on Integrated Circuits (ISIC 2011), Singapore, Dec. 12-14. IEEE, 272−275.
1.1.
2010
Sudnitson, Alexander; Mihhailov, Dmitri; Kruus, Margus (2010). Project-Oriented Approach to Low-Power Topics in Advanced Digital Design Course. Electronics and Electrical Engineering, 151−154.
3.1.
2010
Sagahyroon, F.; Aloul, A.; Sudnitson, A. (2010). Low Power State Assignment Using ILP Techniques. The 15th IEEE Mediterranean Electrotechnical Conference – MELCON-2010. Valletta, Malta, April 25-28, 2010. IEEE, 850−855.
3.1.
2010
Mihhailov, D.; Sudnitson, A.; Tarletski, K. (2010). Web-Based Tool for FSM Encoding Targeting Low-Power FPGA Implementation. The 27th International Conference on Microelectronics– MIEL-2010. Nis, Serbia, May 16-19, 2010. IEEE, 349−352.
3.1.
2010
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2010). Parallel FPGA-based Implementation of Recursive Sorting Algorithms. The 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010), Cancun, Mexico, Dec. 13-15, 2010. IEEE Computer Society Press, 121−126.10.1109/ReConFig.2010.30.
3.1.
2010
Mihhailov, D.; Sklyarov, V.; Skliarova, I.; Sudnitson, A. (2010). Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules. Proceedings : 2010 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, 13–15 December 2010. Ed. Viktor Prasanna, Juergen Becker, and René Cumplido. IEEE Computer Society Press, 436−441.10.1109/ReConFig.2010.29.
3.1.
2010
Mihhailov, D.; Sklyarov, V.; Skliarova, J.; Sudnitson, A. (2010). Optimization of FPGA-based Circuits for Recursive Data Sorting. BEC 2010 : 12th biennial Baltic Electronics Conference : proceedings of the 12th biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia. Tallinn: IEEE, 129−132.
3.1.
2010
Mihhailov, Dmitri; Sklyarov, Valery; Skliarova, Iouliia; Sudnitson, Alexander (2010). Hardware Implementation of Recursive Algorithms. 53rd IEEE International Midwest Symposium on Circuits and Systems - IEEE MWSCAS 2010, Seattle, WA, USA, August 1-4, 2010. IEEE, 225−228.
3.1.
2009
Sudnitson, Alexander; Mihhailov, Dmitri; Kruus, Margus (2009). Cooperation of FPGA-Based Educational Boards and Web-Based Point Design Tools for Research and Education. IFIP EduTech’09International Workshop, Florianopolis- Brazil, Oct.15-16.
3.1.
2009
Sudnitson, A.; Mihhailov, D.; Kruus, M.; Tarletski, K. (2009). FSM Decomposition with Application to FPGA Synthesis. Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing: International Conference on Computer Systems and Technologies-CompSysTech’09, Ruse, Bulgaria. Ed. B. Rachev, A. Smrikarov. ACM, IV.4.1−IV.4.6. (ACM International Conference Proceeding Series; 433).
3.1.
2009
Sudnitson, Alexander; Mihhailov, Dimitri; Kruus, Margus (2009). Advanced Topics of FSM Design Using FPGA Educational Boards and Web-Based Tools. IEEE East-West Design & Test Symposium, Moscow, Russia. 446−449.
3.1.
2008
Mihhailov, D.; Kruus, M.; Sudnitson, A. (2008). FPGA Platform Based Digital Design Education. Proceedings of the 9th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing: International Conference on Computer Systems and Technologies (CompSysTech’2008), Gabrovo, Bulgaaria. Ed. B. Rachev, A. Smrikarov. ACM, IV.1−IV.6. (ACM International Conference Proceeding Series; 374).
3.1.
2008
Devadze, Sergei (2008). Software Environment for Synthesis of Testable FSM through Decomposition. IEEE 26th International Conference on Microelectronics (MIEL 2008), Nis, Serbia. 433−436.
3.1.
2008
Ellervee, P.; Reinsalu, U.; Arhipov, A.; Ivask, E.; Tammemäe, K.; Evartson, T.; Sudnitson, A. (2008). HDL-s and FPGA-s in Digital Design Education. The 19th EAEEIE Annual Conference, Tallinn, Estonia, June 2008. 37−41.
3.1.
2007
Sudnitson, Alexander; Devadze, Sergei (2007). Web-Based Computer Aided Design Support of Finite State Machine Additive Decomposition for Low Power. 5th IEEE East-West Design & Test International Symposium. 494−498.
3.2.
2007
Sudnitsõn, A. (2007). Computer Engineering. In: PhD in Computer Science, Computer Engineering, Software Engineering, Information Systems (121−192).. European Thematic Network 114046-CP-1-BG-ERASMUS-TN. Publishing Company at the University of Rousse..
3.2.
2006
Wuttke, H.-D.; Sudnitson, A.; Henke, K (2006). E-Learning Tools for Teaching the Design and Validation of "Finite State Machines"". In: E-Learning and the Knowledge Society (327−341).. Gent, Belgia: Communication and Cognition .
3.4.
2006
Sudnitson, Alexander; Kruus, Margus (2006). E-Learning Tools for Teaching the Decomposition Based Digital Synthesis. EWME 2006 Proceedings (6-th European Workshop on Microelectronics Education), Stockholm, Sweden, 2006. Stockholm, Sweden: Royal Institue of Technology KTH, 63−66.
3.4.
2006
Smrikarov, A.; Smrikarova, S.; Kruus, M.; Sudnitson, A. (2006). European Thematic Network for Doctoral Education in Computing. Annex of Advances in Current Natural Sciences, Moscow: Academy of Natural Sciences: 33d International Conference on Information Technologies in Science, Education, Telecommunication, Business (IT+SE’2006), Gurzuf, Ukraine. 339−340.
3.4.
2006
Sudnitson, Alexander; Sergei, Devadze (2006). Computer Aided Design Support of FSM Multiplicative Decomposition. IEEE East-West Design&Test International Workshop (EWDTW'06), Sochi, Russia. 241−246.
3.1.
2005
"Devadze, Sergei;Sudnitsõn, Aleksander" (2005). FSM decomposition software for education and research. Proc. IEEE EUROCON 2005 International Conference on Computer as a tool : Belgrade, Serbia & Montenegro. Belgrad: TTY puuduv kirjastus, 839−842.
3.2.
2005
Sudnitsõn, Aleksander (2005). Research and training environment for decomposition-based logical design. In: COMMUNICATION&COGNITION (3.12.1−3.12.7).. Ghent: TTY puuduv kirjastus.
3.4.
2005
Jutman, A.; Rosin, V.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2005). A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard. Proc. of 16th EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering: Lappeenranta, Finland, June 6-8, 2005.
3.4.
2005
Jutman, A.; Kruus, M.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2005). Web-Based Software Package for e-Learning and Research Training in Digital System design. Proc. 32nd International Conference on Information Technologies in Science, Education, Telecommunication, Business: IT+SE'2005, Gurzuf, Ukraine. 306−308.
3.4.
2005
"Fomina, Jelena;Sudnitsõn, Aleksander" (2005). Extended finite state machine decomposition for low power. Proceedings 19th International Conference on Systems for Automation of Engineering and Research : SAER'2005 : Varna, Bulgaria, 2005. Varna, 126−131.
1.2.
2004
Kruus, M.; Lensen, H.; Sudnitson, A. (2004). Digital Design at Microarchtectural Level Based on Quality Relationship Measures. Advances in Current Natural Sciences, 5, 1, 29−31.
3.1.
2004
Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2004). E-Learning Environment in the Area of Digital Microelectronics. Proc. of Int. Conf. on Information Technology Based Higher Education and Training: ITHET’04, Istanbul, Turkey, May 31 – June 2, 2004. IEEE, 278−283.
3.1.
2004
"Fomina, Jelena;Sudnitsõn, Aleksander;Vasiliev, Roman" (2004). Optimization of FSMs network by new encoding strategy. BEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia. Tallinn: Tallinn University of Technology, 119−122.
3.1.
2004
Sudnitson, A. (2004). Register transfer low power design based on controller decomposition. 2: 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716). Piscataway, NJ, USA. 735−738. (IEEE; 04TH8716).
3.4.
2004
"Fomina, Jelena;Sudnitsõn, Aleksander" (2004). Information relationships for decomposition of finite state machine. East-West Design & Test Workshop. 41−47.
3.4.
2004
"Fomina, Jelena;Sudnitsõn, Aleksander;Vasiliev, Roman" (2004). FSM's network encoding guided by information relationship measure. 6th International Workshop on Boolean Problems. Freiberg, Germany: TTY puuduv kirjastus, 55−62.
3.4.
2004
Fomina, E.; Ellervee, P.; Kruus, M.; Sudnitson, A; Tammemae, K. (2004). Digital synthesis tools for education and research. The 18th International Conference on Systems for Automation of Engineering and Research (SAER'2004), Varna, Bulgaria, 2004.. 160−164.
3.4.
2004
Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2004). Asynchronous E-Leaning Resources for Hardware Design Issues. Proc. of the International Conference on Computer Systems and Technologies: CompSysTech'2004, Sofia, Bulgaria, 2004. 1−6.
3.1.
2003
Devadze, Sergei; Fomina, Jelena; Kruus, Margus; Sudnitsõn, Aleksander (2003). Web-based system for sequential machines decomposition. In: EUROCON 2003. Computer as a Tool. (57−61).. [S. l.]: IEEE.
3.1.
2003
Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2003). Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test. Proc. of 4th International Conference on Information Technology Based Higher Education and Training: ITHET'03, Marrakech, Morocco, July 7-9, 2003. 397−401.
3.1.
2003
Fomina, E.; Keevallik, A.; Kruus, M.; Sudnitson, A. (2003). A decomposition procedure for register-transfer level power management. Proceedings of the International Conference on Computer Systems and Technologies (e-Learning) (1.2−1.6).. Sofia: Bulgarian Academy of Science.
3.4.
2003
Jutman, A.; Sudnitson, A.; Ubar, R. (2003). Web-Based Training System for Teaching Principles of Boundary Scan Technique. Proc. 14th EAEEIE Conference on Innovation in Education for Electrical and Information Engineering: Gdansk, Poland, June 16-18, 2003.
3.4.
2003
Jutman, A.; Sudnitson, A.; Ubar, R. (2003). Digital Design Learning System Based on Java Applets. Proc. 4th Annual Conference of the LTSN Centre for Information and Computer Sciences: NUI Galway, Ireland, August 26-28, 2003. 183−187.
3.4.
2003
Jutman, A.; Sudnitson, A.; Ubar, R. (2003). Web-based Applet for Teaching Boundary Scan Standard IEEE 1149.1. Proc. of 10th International Conference on Mixed Design of Integrated Circuits and Systems: MIXDES'03, Lodz, Poland, June 26-28, 2003. 584−589.
3.4.
2003
"Sudnitsõn, Aleksander;Jamšanov, A." (2003). A FSM decomposition method for mixed synchronous/asynchronous implementation. Proc. 17th International Conference on Systems for Automation of Engineering and Research : SAER'2003 : Varna, Bulgaria, 2003. 37−41.
3.1.
2002
Fomina, E.; Keevallik, A.; Kruus, A.; Sudnitson, A. (2002). Web-based tools for finite state machine decomposition with analysis of information flows. BEC 2002. Proceedings of the 8th Biennial Baltic Electronics Conference: 8th Biennial Baltic Electronics Conference. Tallinn: Tallinn Technical University, 165−168.
3.1.
2002
Sudnitson, A. (2002). Computational kernel extraction for synthesis of power-managed sequential components. 2: ICECS 2002. 9th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.02EX611). Piscataway, NJ, USA. IEEE, 749−752.
3.1.
2002
Sudnitson, A. (2002). An approach to synthesis of mixed synchronous/asynchronous digital devices. 2: 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595). Piscataway, NJ, USA. IEEE, 695−698.
3.1.
2002
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2002). Java Technology Based Training System for Teaching Digital Design and Test. Proc. of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002: 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002. 283−286.
3.1.
2002
Fomina, E.; Keevallik, A.; Sudnitson, A (2002). Low power synthesis based on information theoretic measures. 23rd International Conference on Microelectronics. Proceedings, 2: 23rd International Conference on Microelectronics. Piscataway, NJ, USA: IEEE, 699−702.
3.2.
2002
Kruus, Margus; Lensen, Harri; Sudnitsõn, Aleksander (2002). Web-based tools for decomposition-oriented digital design. 1: MEET/MARIND'2002 : proceedings of First International Congress on Mechanical and Electrical Engineering and Technology and Fourth International Conference on Marine Industry, 07-11 October 2002, Varna Bulgaria. Varna: TTY puuduv kirjastus, 261−266.
3.4.
2002
Devadze, S.; Jutman, A.; Kruus, M.; Sudnitson, A.; Ubar, R. (2002). Web Based Tools for Synthesis and Testing of Digital Devices. Proc. International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002: International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002. I.91−I.96.
3.4.
2002
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R. (2002). Web-based training system for teaching basics of RT-level Digital Design, Test, and Design for Test. Proc. of 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002: 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002. 699−704.
3.4.
2002
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2002). Teaching Digital RT-Level Self-Test using a Java Applet. 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002. 322−328.
3.4.
2002
"Fomina, Jelena;Keevallik, Andres;Sudnitsõn, Aleksander" (2002). Entropic analysis of finite state mashines' networks. IEEE 5th International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2002). Brno: Brno University of Technology, 244−251.
3.4.
2002
Sudnitsõn, Aleksander (2002). Integrating dynamic power management in the register transfer level synthesis. 1: MEET/MARIND'2002 : proceedings of First International Congress on Mechanical and Electrical Engineering and Technology and Fourth International Conference on Marine Industry, 07-11 October 2002, Varna Bulgaria. Varna, 267−274.
3.2.
2001
Devadze, Sergei; Kruus, Margus; Sudnitsõn, Aleksander (2001). Web-based software implementation of finite state machine decomposition for design and education. Proc. International Conference on Computer Systems and Technologies : CompSys'2001 : Sofia, Bulgaria, 2001.
3.4.
2001
Sudnitsõn, Aleksander (2001). Finite state machines with datapath partitioning for low power synthesis. Proceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 2000. [S. l.], 163−168.
3.4.
2001
Sudnitsõn, Aleksander (2001). Functional partitioning for register transfer level low power synthesis. ECS'01 : proceedings of the 3rd Electronic Circuits and Systems Conference : September 5-7, 2001, Bratislava, Slovakia. [S. l.], 73−76.
3.4.
2001
Kruus, M.; Lensen, H.; Sudnitsõn, A. (2001). Synthesis of Sequential Circuits with Dynamic Power Management. Proceedings of RTUCET '01, Oct. 12, 2001, Riga.
3.4.
2000
"Sudnitsõn, Aleksander;Levenko, Aleksei;Andreev, Dmitri" (2000). Java-based system for finite state machine decomposition. In: 45th International Scientific Colloquium IWK2000 (961−965).. Ilmenau, Germany: Technische Universität Ilmenau.
3.4.
2000
Sudnitsõn, Aleksander (2000). Partition search problem for finite state machine decomposition. 45th International Scientific Colloquium IWK2000. [Ilmenau]: Frank Cass, 673−678.
3.4.
2000
Sudnitsõn, Aleksander (2000). Finite state machine synthesis for low power using input-disabling precomputation architectures. "The 7th Biennial Conference on Electronics and Microsystem Technology ""Baltic Electronics Conference"" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings". [Tallinn]: Tallinn Technical University, 137−140.
29.04.2019

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ProgrammLiikNumberNimiProjekti algusProjekti lõppVastutav täitjaAsutusFinantseerijapoolne rahastamine
SFSF0142508s03Digitaalsüsteemide disain ja test01.01.200331.12.2007Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond658 321,94 EUR
MUUT244 (0140244s98)Digitaalsüsteemide projekteerimise ja diagnostika alased uuringud, väljatöötlused ja rakendused01.01.199831.12.2002Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 417 982,18 EUR
MUUV330Euroopa temaatiline võrgustik 'Arvutialane doktoriõpe' (ETN DEC)01.10.200401.10.2007Aleksander SudnitsõnTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool 11 504,10 EUR
MUUVERT403Euroopa temaatiline võrgustik arvutialase hariduse õpetamiseks, uuringuteks ja uuendusteks (ETN TRICE)01.10.200810.10.2011Aleksander SudnitsõnTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool 5 997,47 EUR
MUUVFP15055Horisont 2020 Twinning projekt TTÜ võimekuse tõstmiseks nanoelektroonikal põhinevate usaldusväärsete küberfüüsikaliste süsteemide valdkonnas (TUTORIAL)01.01.201631.12.2018Jaan RaikTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 518 000,00 EUR
TKTAR8077Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus CEBE07.07.200831.08.2015Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut2 066 263,60 EUR
MUUV152Kaugõppe tarkvara digitaalsüsteemide disaini ja testi valdkonnas, DILDIS01.01.199931.12.2005Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 24 000,04 EUR
MUUG4876 (ETF4876)Lõplike automaatide dekompositsiooniliste sünteesimeetodite arendamine ja vastavate WWW-põhiste disainivahendite loomine01.01.200131.12.2002Aleksander SudnitsõnTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool 10 801,07 EUR
ETFETF9251Rekonfigureeritav protsessor kombinatoorsete ülesannete lahendmiseks puulaadsete andmestruktuuride baasil01.01.201231.12.2015Aleksander SudnitsõnTallinna Tehnikaülikool, Infotehnoloogia teaduskond28 320,00 EUR
ETFETF8478Riistvara funktsionaalne verifitseerimine ja silumine01.01.201031.12.2013Maksim JenihhinTallinna Tehnikaülikool, Infotehnoloogia teaduskond55 219,32 EUR
MUUEITSA8Sardsüsteemide õppe-ja teaduslabori loomine01.07.200930.11.2012Gert JervanTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut166 170,29 EUR
MUUVERT662Tulevane arvutialane haridus ja praktiline täiendõpe: kuidas toetada õpetamist igal ajal ja igal pool01.10.201330.09.2016Aleksander SudnitsõnTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool 4 500,00 EUR
SFSF0140041s08Töökindlate sardsüsteemide disain01.01.200831.12.2013Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond1 504 530,37 EUR
IUTIUT19-1Usaldusväärsed mitmetuumalised arvutisüsteemid01.01.201431.12.2019Jaan RaikTallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut1 572 000,00 EUR
MUUVFP382Usaldusväärsete süsteemide kompetentsikeskus01.03.200929.02.2012Gert JervanTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut983 099,97 EUR
MUUV170Uurimis- ja õppetöö meetodid valdkonnas 'Ühekiibisüsteemide disain'01.12.200130.11.2004Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 124 627,71 EUR
MUUV195Virtuaalse infotehnoloogia teadusliku uurimis- ja arendustöö tippkeskuse rajamine01.11.200231.08.2005Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 137 346,13 EUR
MUUG5643 (ETF5643)Võrreldavatele kvaliteedihinnangutele põhinev digitaalsüsteemide dekompositsioon01.01.200331.12.2005Aleksander SudnitsõnTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool 8 308,51 EUR