Anton Tšepurov

https://www.etis.ee/CV/Anton_Tšepurov/est
1.01.1985
anton.chepurov@gmail.com

Teenistuskäik

Töökohad ja ametid
01.09.2012–31.08.2013   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool , nooremteadur (0,25)
01.03.2011–31.08.2012   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool , Teadur (0,25)
2005–2005   
Hansapank AS, Tarkvaraarendaja (1,00)
 
 
Haridustee
2006–2008   
Tallinna Tehnikaülikool (tehnikateaduse magistri kraad, kiitusega; arvuti- ja süsteemitehnika õppekava)
2003–2006   
Tallinna Tehnikaülikool (2006 - tehnikateaduse bakalaureuse kraad; arvuti- ja süsteemitehnika õppekava)
2000–2003   
Tartu Annelinna Gümnaasium

Kvalifikatsioon

Teaduskraadid
Anton Tšepurov, doktorikraad, 2013, (juh) Jaan Raik; Maksim Jenihhin, Hardware Modeling for Design Verification and Debug (Riistvara modelleerimine disaini verifitseerimise ja silumise jaoks), Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool.
Anton Tšepurov, magistrikraad, 2008, (juh) Jaan Raik; Maksim Jenihhin, Converting VHDL design to High-Level Decision Diagrams Model (VHDL riistvara kirjelduskeelsete projektide teisendamine kõrgtaseme otsustusdiagrammide mudelile), Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool.
 
 
Teaduspreemiad ja tunnustused
2011, Anton Tšepurov, "Tiigriülikooli" stipendium IKT doktorantidele (EITSA)
2010, Anton Tšepurov, "Tiigriülikooli" stipendium IKT doktorantidele (EITSA)
2009, Anton Tšepurov, "Tiigriülikooli" stipendium IKT doktorantidele (EITSA)
2008, Anton Tšepurov, "Tiigriülikooli" stipendium IKT doktorantidele (EITSA)
 
 
Teadustöö põhisuunad
VALDKOND: 4. Loodusteadused ja tehnika; 4.7. Info- ja kommunikatsioonitehnoloogia; PÕHISUUND: Arvutiteadus (Digitaalsüsteemide testimine ja diagnostika)

Lõppenud projektid

Publikatsioonid

Klass
Aasta
Publikatsioon
 
1.1.
2013
Jenihhin, M.; Tšepurov, A.; Tihhomirov, V.; Raik, J.; Hantson, H.; Ubar, R.; Bartsch, G.; Meza-Escobar, J.H.; Wuttke, H.D. (2013). Automated Design Error Localization in RTL Designs. IEEE Design & Test of Computers, 1−13.
1.1.
2013
Raik, Jaan; Repinski, Urmas; Tšepurov, Anton; Hantson, Hanno; Ubar, Raimund; Jenihhin, Maksim. (2013). Automated design error debug using high-level decision diagrams and mutation operators. Microprocessors and Microsystems: Embedded Hardware Design, 37 (4), 1−10.
3.1.
2013
Tihhomirov, Valentin; Tšepurov, Anton; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund (2013). Assessment of Diagnostic Test for Automated Bug Localization. Proc. of 14th IEEE Latin-American Test Workshop: 14th IEEE Latin-American Test Workshop (LATW), Cordoba, Argentina, April 3-5, 2013. 1−6.10.1109/LATW.2013.6562665.
3.4.
2013
Tihhomirov, Valentin; Tšepurov, Anton; Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2013). VHDL Design Debug Framework Based on zamiaCAD. DATE 2013 University Booth: Design Automation and Test in Europe, Grenoble, France, March 18-22, 2013. 1−1.
3.1.
2012
Raik, J.; Drenkhan, T.; Jenihhin, M.; Viilukas, T.; Karputkin, A.; Tšepurov, A.; Ubar, R. (2012). Generating Directed Tests for C Programs using RTL ATPG. Proceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12): IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12), Niigata, Japan, November 22-23, 2012. 1−6.
3.1.
2012
Tšepurov, Anton; Tihhomirov, Valentin; Jenihhin, Maksim; Raik, Jaan; Bartsch, Günter; Meza Escobar, Jorge Hernan; Wuttke, Heinz-Dietrich. (2012). Localization of Bugs in Processor Designs Using zamiaCAD Framework. 13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions, Austin, USA, December 10–12, 2012. IEEE, 1−6.
3.1.
2012
Tšepurov, Anton; Bartsch, Günter; Dorsch, Rainer; Jenihhin, Maksim; Raik, Jaan; Tihhomirov, Valentin (2012). A Scalable Model Based RTL Framework zamiaCAD for Static Analysis. 2012 IEEE/IFIP 20th International Conference on Very Large Scale Integration (VLSI-SoC), 7-10 October 2012, Santa Cruz, USA. IEEE, 171−176.10.1109/VLSI-SoC.2012.6379025.
3.4.
2012
Chepurov, Anton; Tihhomirov, Valentin; Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2012). Applications of the Open Source HW Design Framework zamiaCAD. DATE 2012 University Booth: Design Automation and Test in Europe, Dresden, Germany, March 12-16, 2012. 1−1.
3.1.
2011
Raik, Jaan; Repinski, Urmas; Jenihhin, Maksim; Chepurov, Anton (2011). High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis. Design and Test Technology for Dependable Systems-on-Chip (294−309).. IGI Publishing.
1.2.
2010
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2010). Application of High-Level Decision Diagrams for Simulation-Based Verification tasks. Estonian Journal of Engineering, 16 (1), 56−77.
3.1.
2010
Raik, Jaan; Repinski, Urmas; Ubar, Raimund; Jenihhin, Maksim; Chepurov, Anton (2010). High-level design error diagnosis using backtrace on decision diagrams. 28th Norchip Conference 15-16 November 2010, Tampere, FINLAND. IEEE,.
3.1.
2010
Hantson, Hanno; Raik, Jaan; di Guglielmo, Giuseppe; Jenihhin, Maksim; Chepurov, Anton; Fummi, Franco; Ubar, Raimund (2010). Mutation Analysis with High-Level Decision Diagrams. 11th Latin-American TestWorkshop, Punta del Este, Uruguay, 28-31.03.2010. IEEE Computer Society Press, 1−6.10.1109/LATW.2010.5550336.
3.2.
2010
Ubar, Raimund; Jutman, Artur; Raik, Jaan; Devadze, Sergei; Aleksejev, Igor; Chepurov, Anton; Chertov, Anton; Kostin, Sergei; Orasson, Elmet; Wuttke, H.-D. (2010). E-Learning Environment for WEB-Based Study of Testing. Proc. of the 8th European Workshop on Microelectronics Education - EWME 2010: 8th European Workshop on Microelectronics Education - EWME 2010. Saksamaa, Darmstadt, 47−52.
3.4.
2010
Tsepurov, Anton; Jenihhin, Maksim; Raik, Jaan (2010). Simulator for ZamiaCAD Integrated Hardware Design Environment. DATE 2010 University Booth: Design Automation and Test in Europe, Dresden, Germany, March 8-12, 2010. 1−2.
1.1.
2009
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2009). PSL Assertion-Checking Using Temporally Extended High-Level Decision Diagrams. Journal of Electronic Testing-Theory and Applications, 25 (6), 1−12.
3.1.
2009
Jenihhin, Maksim; Raik, Jaan; Chepurov, Anton; Reinsalu, Uljana; Ubar, Raimund (2009). High-Level Decision Diagrams based Coverage Metrics for Verification and Test. In: Proceedings of 10th IEEE Latin American Test Workshop (1−6).. IEEE.
3.1.
2009
Jenihhin, M.; Raik, J.; Chepurov, A.; Reinsalu, U.; Ubar, R. (2009). Code Coverage Analysis for Concurrent Programming Languages Using High-Level Decision Diagrams. Proceedings of the 12th European Workshop on Dependable Computing, EWDC 2009, Toulouse, France, May 14-15, 2009: 12th European Workshop on Dependable Computing, EWDC 2009, Toulouse, France, May 14-15, 2009. 1−4.
3.1.
2009
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2009). Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams. East-West Design & Test Symposium: East-West Design & Test Symposium, Moscow, Sept.18-21, 2009. 13−16.
3.1.
2008
Jutman, A.; Tsertov, A.; Tsepurov, A.; Aleksejev, I.; Ubar, R.; Wuttke, H.-D. (2008). Teaching Digital Test with BIST Analyzer. 19th EAEEIE Annual Conference: Formal Proceedings: 19th EAEEIE Annual Conference June 29 - July 2, 2008 Tallinn, Estonia. Tallinn, Estonia: IEEE, 123−128.
3.1.
2008
Raik, J.; Jenihhin, M.; Chepurov, A.; Reinsalu, U.; Ubar, R. (2008). APRICOT: a Framework for Teaching Digital Systems Verification. In: 19th EAEEIE Annual Conference (1−6).. IEEE.
3.1.
2008
Jenihhin, M.; Raik, J.; Ubar, R.; Chepurov, A. (2008). On reusability of verification assertions for testing. In: 11th Biennial Baltic Electronics Conference (151−154).. IEEE.
3.1.
2008
Chepurov, Anton; Di Guglielmo, Giuseppe; Fummi, Franco; Pravadelli, Graziano; Raik, Jaan; Ubar, Raimund; Viilukas, Taavi (2008). Automatic Generation of EFSMs and HLDDs for Functional ATPG. In: 11th Biennial Baltic Electronics Conference (143−146).. IEEE.
3.1.
2008
Minakova, K.; Reinsalu, U.; Chepurov, A.; Raik, J.; Jenihhin, M.; Ubar, R.; Ellervee, P. (2008). High-Level Decision Diagram Manipulations for Code Coverage Analysis. The 11th Biennial Baltic Electronics Conference (BEC'08), Tallinn, Estonia, Oct. 2008. 207−210.
3.1.
2008
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2008). Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. Proceedings of the 13th IEEE European Test Symposium. Los Alamitos, USA: IEEE Computer Society Press, 61−68.
3.2.
2008
Raik, Jaan; Ubar, Raimund; Jenihhin, Maksim; Chepurov, Anton (2008). PSL Assertion Checking with Temporally Extended High-Level Decision Diagrams. 9th IEEE Latin American Test Workshop , February 17-20, 2008, Puebla, Mexico. IEEE, 49−54.
3.1.
2007
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2007). Assertion Checking with PSL and High-Level Decision Diagrams. In: Proceedings of the IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) (-).. Beijing, China: IEEE Computer Society Press.
3.1.
2007
Jutman, A.; Tsertov, A.; Tsepurov, A.; Aleksejev, I.; Ubar, R.; Wuttke, H-D. (2007). BIST Analyzer: a Training Platform for SoC Testing. Frontiers in education conference - global engineering: knowledge without borders, opportunities without passports, 2007. FIE '07: 37th Annual Frontiers in Education Conference, Milwaukee, USA, Oct 10-13 2007. IEEE Computer Society Press, 1534−1539.
5.04.2018

Anton Tšepurov

https://www.etis.ee/CV/Anton_Tšepurov/eng
1.01.1985
anton.chepurov@gmail.com

Career

Institution(s) and position(s)
01.09.2012–31.08.2013   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Test and Verification, Junior Researcher (0,25)
01.03.2011–31.08.2012   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Test and Verification, Researcher (0,25)
2005–2005   
Hansabank, Software developer (1,00)
 
 
Education
2006–2008   
Tallinn University of Technology (MA / MSc Student, Cum Laude, Faculty of Information Technology, Department of Computer Engineering, Chair Of Computer Engineering and Diagnostics)
2003–2006   
Tallinn University of Technology (2006 - Bachelor degree in Computer Science)
2000–2003   
Tartu Annelinna High School

Qualifications

Academic degrees
Anton Tšepurov, Doctor's Degree, 2013, (sup) Jaan Raik; Maksim Jenihhin, Hardware Modeling for Design Verification and Debug, Tallinn University of Technology School of Information Technologies, Department of Computer Engineering Chair of Computer Systems Test and Verification.
Anton Tšepurov, Master's Degree, 2008, (sup) Jaan Raik; Maksim Jenihhin, Converting VHDL design to High-Level Decision Diagrams Model, Tallinn University of Technology School of Information Technologies, Department of Computer Engineering Chair of Computer Systems Test and Verification.
 
 
Honours & awards
2011, Anton Tšepurov, "Tiger University" scholarship for ICT PhD students (EITF)
2010, Anton Tšepurov, "Tiger University" scholarship for ICT PhD students (EITF)
2009, Anton Tšepurov, "Tiger University" scholarship for ICT PhD students (EITF)
2008, Anton Tšepurov, "Tiger University" scholarship for ICT PhD students (EITF)
 
 
Field of research
FIELD OF RESEARCH: 4. Natural Sciences and Engineering; 4.7. Telecommunications
 
 

Completed projects

Publications

Category
Year
Publication
 
1.1.
2013
Jenihhin, M.; Tšepurov, A.; Tihhomirov, V.; Raik, J.; Hantson, H.; Ubar, R.; Bartsch, G.; Meza-Escobar, J.H.; Wuttke, H.D. (2013). Automated Design Error Localization in RTL Designs. IEEE Design & Test of Computers, 1−13.
1.1.
2013
Raik, Jaan; Repinski, Urmas; Tšepurov, Anton; Hantson, Hanno; Ubar, Raimund; Jenihhin, Maksim. (2013). Automated design error debug using high-level decision diagrams and mutation operators. Microprocessors and Microsystems: Embedded Hardware Design, 37 (4), 1−10.
3.1.
2013
Tihhomirov, Valentin; Tšepurov, Anton; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund (2013). Assessment of Diagnostic Test for Automated Bug Localization. Proc. of 14th IEEE Latin-American Test Workshop: 14th IEEE Latin-American Test Workshop (LATW), Cordoba, Argentina, April 3-5, 2013. 1−6.10.1109/LATW.2013.6562665.
3.4.
2013
Tihhomirov, Valentin; Tšepurov, Anton; Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2013). VHDL Design Debug Framework Based on zamiaCAD. DATE 2013 University Booth: Design Automation and Test in Europe, Grenoble, France, March 18-22, 2013. 1−1.
3.1.
2012
Raik, J.; Drenkhan, T.; Jenihhin, M.; Viilukas, T.; Karputkin, A.; Tšepurov, A.; Ubar, R. (2012). Generating Directed Tests for C Programs using RTL ATPG. Proceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12): IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12), Niigata, Japan, November 22-23, 2012. 1−6.
3.1.
2012
Tšepurov, Anton; Tihhomirov, Valentin; Jenihhin, Maksim; Raik, Jaan; Bartsch, Günter; Meza Escobar, Jorge Hernan; Wuttke, Heinz-Dietrich. (2012). Localization of Bugs in Processor Designs Using zamiaCAD Framework. 13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions, Austin, USA, December 10–12, 2012. IEEE, 1−6.
3.1.
2012
Tšepurov, Anton; Bartsch, Günter; Dorsch, Rainer; Jenihhin, Maksim; Raik, Jaan; Tihhomirov, Valentin (2012). A Scalable Model Based RTL Framework zamiaCAD for Static Analysis. 2012 IEEE/IFIP 20th International Conference on Very Large Scale Integration (VLSI-SoC), 7-10 October 2012, Santa Cruz, USA. IEEE, 171−176.10.1109/VLSI-SoC.2012.6379025.
3.4.
2012
Chepurov, Anton; Tihhomirov, Valentin; Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2012). Applications of the Open Source HW Design Framework zamiaCAD. DATE 2012 University Booth: Design Automation and Test in Europe, Dresden, Germany, March 12-16, 2012. 1−1.
3.1.
2011
Raik, Jaan; Repinski, Urmas; Jenihhin, Maksim; Chepurov, Anton (2011). High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis. Design and Test Technology for Dependable Systems-on-Chip (294−309).. IGI Publishing.
1.2.
2010
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2010). Application of High-Level Decision Diagrams for Simulation-Based Verification tasks. Estonian Journal of Engineering, 16 (1), 56−77.
3.1.
2010
Raik, Jaan; Repinski, Urmas; Ubar, Raimund; Jenihhin, Maksim; Chepurov, Anton (2010). High-level design error diagnosis using backtrace on decision diagrams. 28th Norchip Conference 15-16 November 2010, Tampere, FINLAND. IEEE,.
3.1.
2010
Hantson, Hanno; Raik, Jaan; di Guglielmo, Giuseppe; Jenihhin, Maksim; Chepurov, Anton; Fummi, Franco; Ubar, Raimund (2010). Mutation Analysis with High-Level Decision Diagrams. 11th Latin-American TestWorkshop, Punta del Este, Uruguay, 28-31.03.2010. IEEE Computer Society Press, 1−6.10.1109/LATW.2010.5550336.
3.2.
2010
Ubar, Raimund; Jutman, Artur; Raik, Jaan; Devadze, Sergei; Aleksejev, Igor; Chepurov, Anton; Chertov, Anton; Kostin, Sergei; Orasson, Elmet; Wuttke, H.-D. (2010). E-Learning Environment for WEB-Based Study of Testing. Proc. of the 8th European Workshop on Microelectronics Education - EWME 2010: 8th European Workshop on Microelectronics Education - EWME 2010. Saksamaa, Darmstadt, 47−52.
3.4.
2010
Tsepurov, Anton; Jenihhin, Maksim; Raik, Jaan (2010). Simulator for ZamiaCAD Integrated Hardware Design Environment. DATE 2010 University Booth: Design Automation and Test in Europe, Dresden, Germany, March 8-12, 2010. 1−2.
1.1.
2009
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2009). PSL Assertion-Checking Using Temporally Extended High-Level Decision Diagrams. Journal of Electronic Testing-Theory and Applications, 25 (6), 1−12.
3.1.
2009
Jenihhin, Maksim; Raik, Jaan; Chepurov, Anton; Reinsalu, Uljana; Ubar, Raimund (2009). High-Level Decision Diagrams based Coverage Metrics for Verification and Test. In: Proceedings of 10th IEEE Latin American Test Workshop (1−6).. IEEE.
3.1.
2009
Jenihhin, M.; Raik, J.; Chepurov, A.; Reinsalu, U.; Ubar, R. (2009). Code Coverage Analysis for Concurrent Programming Languages Using High-Level Decision Diagrams. Proceedings of the 12th European Workshop on Dependable Computing, EWDC 2009, Toulouse, France, May 14-15, 2009: 12th European Workshop on Dependable Computing, EWDC 2009, Toulouse, France, May 14-15, 2009. 1−4.
3.1.
2009
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2009). Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams. East-West Design & Test Symposium: East-West Design & Test Symposium, Moscow, Sept.18-21, 2009. 13−16.
3.1.
2008
Jutman, A.; Tsertov, A.; Tsepurov, A.; Aleksejev, I.; Ubar, R.; Wuttke, H.-D. (2008). Teaching Digital Test with BIST Analyzer. 19th EAEEIE Annual Conference: Formal Proceedings: 19th EAEEIE Annual Conference June 29 - July 2, 2008 Tallinn, Estonia. Tallinn, Estonia: IEEE, 123−128.
3.1.
2008
Raik, J.; Jenihhin, M.; Chepurov, A.; Reinsalu, U.; Ubar, R. (2008). APRICOT: a Framework for Teaching Digital Systems Verification. In: 19th EAEEIE Annual Conference (1−6).. IEEE.
3.1.
2008
Jenihhin, M.; Raik, J.; Ubar, R.; Chepurov, A. (2008). On reusability of verification assertions for testing. In: 11th Biennial Baltic Electronics Conference (151−154).. IEEE.
3.1.
2008
Chepurov, Anton; Di Guglielmo, Giuseppe; Fummi, Franco; Pravadelli, Graziano; Raik, Jaan; Ubar, Raimund; Viilukas, Taavi (2008). Automatic Generation of EFSMs and HLDDs for Functional ATPG. In: 11th Biennial Baltic Electronics Conference (143−146).. IEEE.
3.1.
2008
Minakova, K.; Reinsalu, U.; Chepurov, A.; Raik, J.; Jenihhin, M.; Ubar, R.; Ellervee, P. (2008). High-Level Decision Diagram Manipulations for Code Coverage Analysis. The 11th Biennial Baltic Electronics Conference (BEC'08), Tallinn, Estonia, Oct. 2008. 207−210.
3.1.
2008
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2008). Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. Proceedings of the 13th IEEE European Test Symposium. Los Alamitos, USA: IEEE Computer Society Press, 61−68.
3.2.
2008
Raik, Jaan; Ubar, Raimund; Jenihhin, Maksim; Chepurov, Anton (2008). PSL Assertion Checking with Temporally Extended High-Level Decision Diagrams. 9th IEEE Latin American Test Workshop , February 17-20, 2008, Puebla, Mexico. IEEE, 49−54.
3.1.
2007
Jenihhin, M.; Raik, J.; Chepurov, A.; Ubar, R. (2007). Assertion Checking with PSL and High-Level Decision Diagrams. In: Proceedings of the IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07) (-).. Beijing, China: IEEE Computer Society Press.
3.1.
2007
Jutman, A.; Tsertov, A.; Tsepurov, A.; Aleksejev, I.; Ubar, R.; Wuttke, H-D. (2007). BIST Analyzer: a Training Platform for SoC Testing. Frontiers in education conference - global engineering: knowledge without borders, opportunities without passports, 2007. FIE '07: 37th Annual Frontiers in Education Conference, Milwaukee, USA, Oct 10-13 2007. IEEE Computer Society Press, 1534−1539.
5.04.2018
Detailne otsing
  • Leitud 5 kirjet
ProgrammLiikNumberNimiProjekti algusProjekti lõppVastutav täitjaAsutusFinantseerijapoolne rahastamine
ETFETF9429Isetestivad usaldatavad mesokroonsed kiipvõrgud01.01.201231.12.2015Jaan RaikTallinna Tehnikaülikool, Infotehnoloogia teaduskond33 984,00 EUR
ETFETF8478Riistvara funktsionaalne verifitseerimine ja silumine01.01.201031.12.2013Maksim JenihhinTallinna Tehnikaülikool, Infotehnoloogia teaduskond55 219,32 EUR
ETFETF7894Süsteemitesti meetodid keerukatele trükkplaatidele01.01.200931.12.2012Artur JutmanTallinna Tehnikaülikool, Infotehnoloogia teaduskond44 999,60 EUR
MUULep9007Tehnoloogia arenduskeskus ELIKO projekt 2.2 Sardsüsteemide test, verifitseerimine ja silumine01.09.200830.06.2009Jaan RaikTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 8 500,25 EUR
SFSF0140041s08Töökindlate sardsüsteemide disain01.01.200831.12.2013Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond1 504 530,37 EUR