See veebileht kasutab küpsiseid kasutaja sessiooni andmete hoidmiseks. Veebilehe kasutamisega nõustute ETISe kasutustingimustega. Loe rohkem
Olen nõus

Behrad Niazmand

https://www.etis.ee/CV/Behrad_Niazmand/est
3.12.1986
6202667
55508978
behrad.niazmand@taltech.ee
Research Interests:
• System-on-Chip /Network-on-Chip Design
o Addressing Thermal issues using Adaptive Routing Algorithms
o Working on new Selection Functions
o Distributing Traffic and Temperature using minimal/non-minimal Routing Algorithms
o Extending current Selection Function proposals to Networks with higher dimensions (3D)
o Reconfigurable and Fault-Tolerant Architectures
o Introduction of checkers for Fault Detection in control part of NoC routers
• Computer Architecture
o Studying the Architecture of Multi-Core Processors
• Hardware Modeling and Design
• Computer Networks
• Real-Time Embedded Systems
o Mixed-Criticality Systems

Teenistuskäik

Töökohad ja ametid
07.10.2019–...   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, Teadur (0,10)
01.09.2018–07.10.2019   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, Teadur (1,00)
01.09.2018–24.12.2018   
Delft University of Technology (TU Delft), Visiting researcher (PostDoc) (1,00)
01.01.2017–31.08.2018   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, Nooremteadur (0,75)
06.10.2014–31.12.2016   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Nooremteadur (0,75)
 
 
Haridustee
01.09.2014–16.05.2018   
Töökindluse parandamine kiipvõrkudel põhinevates süsteemides
2010–2012   
M.Sc. in Computer Engineering- Computer Architecture, Science and Research Branch, Islamid Azad University (IAU), Tehran, Iran
2005–2009   
B.Sc. in Computer Hardware Engineering, South Tehran Branch, Islamid Azad University (IAU), Tehran, Iran

Kvalifikatsioon

Teaduskraadid
Behrad Niazmand, doktorikraad, 2018, (juh) Gert Jervan; Jaan Raik, Dependability Improvements of NoC-based Systems (Töökindluse parandamine kiipvõrkudel põhinevates süsteemides), Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut.
 
 
Teaduspreemiad ja tunnustused
2018, Behrad Niazmand, Accepted as one of the 5 candidates for the semi-final McCluskey PhD thesis award at ETS 2018
2016, Behrad Niazmand, Third Co-supervisor for Master Thesis of Apneet Kaur Sandhu, "Online fault detection methodology for control and data path of IP cores, A case study on Bonfire network-on-chip"
2016, Behrad Niazmand, Second Co-supervisor for Master Thesis of Martin Dída, "Performance Analysis of Bonfire Network on Chip"
2016, Behrad Niazmand, Second Co-supervisor for Master Thesis of Tsotne Putkaradze, "Turn Preserving Fault Tolerance Methodology for On-Chip Routers and Implementation on Bonfire Router"
2016, Behrad Niazmand, Assistance for labs for course "Digital Systems Modeling and Synthesis", code IAY0340, instructor : Professor Peeter Ellervee, Spring Semester.
2015, Behrad Niazmand, • Acquired IT Academy Scholarship (sponsored by Skype) for the second year of PhD studies at Tallinn University of Technology.
2014, Behrad Niazmand, • Acquired Tiger University Scholarship from HITSA for the first year of PhD studies at Tallinn University of Technology.
2010, Behrad Niazmand, • Accepted straightly in Master’s Degree at Islamic Azad University (IAU) – Science and Research Campus without passing the national general university entrance exam(Concours Nationale)
2009, Behrad Niazmand, • Acquired a collaborative invention certificate for "Implementing Ethernet Encryption and Decryption Board based on Microcontrollers", Iran
2009, Behrad Niazmand, • Ranked 1st for three semesters among the Computer engineering Department's Hardware students , IAU, South Tehran branch, Iran
 
 
Teadustöö põhisuunad
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.8. Elektrotehnika ja elektroonika; CERCS KLASSIFIKAATOR: T171 Mikroelektroonika ; TÄPSUSTUS: Info- ja kommunikatsioonitehnoloogia (arvuti- ja süsteemitehnika), • System-on-Chip /Network-on-Chip Design o Addressing Thermal issues using Adaptive Routing Algorithms o Working on new Selection Functions o Distributing Traffic and Temperature using minimal/non-minimal Routing Algorithms o Extending current Selection Function proposals to Networks with higher dimensions (3D) o Reconfigurable and Fault-Tolerant Architectures o Introduction of checkers for Fault Detection in control part of NoC routers • Computer Architecture o Studying the Architecture of Multi-Core Processors • Hardware Modeling and Design • Computer Networks • Real-Time Embedded Systems o Mixed-Criticality Systems
 
 
Lisainfo
• Acceptance of the paper titled “Logic-Based Implementation of Fault-Tolerant Routing in 3D Network-on-Chips” in NOCS 2016, Nara, Japan
• Acceptance of the paper titled “SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints” in ReCoSoC 2016, Tallinn, Estonia.
• Acceptance of the paper titled “A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers” to Euromicro DSD conference held in Madeira, Portugal, as a co-author.
• Acceptance of the paper titled “Automated Minimization of Concurrent Online Checkers for Networks-on-Chip” 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015) held in Bremen, Germany as a co-author.
• Acceptance of the paper “A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers” in 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2015) held in Vancouver, Canada, as a co-author.
• Acceptance of the paper “Mixed-Criticality MPSoC Partitioning based on the NoCDepend Dependability Technique” in 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015) held in Bremen, Germany, as a co-author.
• “Extended Checkers for Control Part of Routers in Network-on-Chips”, MEDIAN 2015, Manufacturable and Dependable Multicore Architectures at Nanoscale, DATE Friday Workshop, March 13, 2015, Grenoble, France
• “Extended Checkers for Control Part of Routers in Network-on-Chips”, Info- ja kommunikatsioonitehnoloogia doktorikool (IKTDK) 2014 conference for Doctoral Students in ICT, December 5-6, Rakvere, Estonia.
• "Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips”, 14th Biennial Baltic Electronics Conference (BEC), October 6-8, 2014, Laulasmaa, Estonia.
• Seminar in department of Computer Engineering at Tallinn University of Technology, for practicing for BEC conference
• "Initialization and Installation of DHCP Service in windows Server 2003" Delivered as a term paper for the Computer Networks Lab. at Computer Engineering Department of IAU, 2009.
• "N-way Set-Associative Cache", Delivered as a term paper for Computer architecture Course, Under the supervision of
Dr. A. Broumandnia, at Computer Engineering Department of IAU, 2008.
• "Error Detection and Correction" Delivered as a term paper for Signals and Systems course, Under the supervision of
Dr. A. Broumandnia, at Computer Engineering Department of IAU, 2008.
• “Clock with AVR Microcontroller" Delivered as a course project for Microprocessor II course, under the supervision of
Dr. M. Kazemi Parsa, at Computer Engineering Department of IAU, 2009.

Jooksvad projektid

Lõppenud projektid

Juhendatud väitekirjad

Publikatsioonid

Klass
Aasta
Publikatsioon
 
3.1.
2020
Reinbrecht, Cezar; Hamdioui, Said; Taouil, Mottaqiallah; Niazmand, Behrad; Ghasempouri, Tara; Raik, Jaan; Sepúlveda, Johanna; (2020). LiD-CAT: A Lightweight Detector for Cache Attacks. In: European Test Symposium (ETS) 2020 (Ed.). LiD-CAT: A Lightweight Detector for Cache Attacks. IEEE [ilmumas].
3.1.
2019
Niazmand, Behrad; Payandeh Azad, Siavoosh; Jervan, Gert; Sepúlveda, Johanna; (2019). Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks. In: Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks (672−676). IEEE: IEEE. DOI: 10.1109/DSD.2019.00108.
3.5.
2019
Niazmand, Behrad; Reinbrecht, Cezar; Raik, Jaan; Jervan, Gert; Sepulveda, Johanna (2019). Towards Formal Verification of Cache Access-based Side-Channel Attacks. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, TUZ 2019. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, TUZ 2019, 1−2.
2.3.
2018
Niazmand, B. (2018). Dependability Improvements of NoC-based Systems. (Doktoritöö, Tallinn University of Technology). TTÜ Press: TTU Press.
3.1.
2018
Avramenko, Serhiy; Azad, Siavoosh Payandeh; Esposito, Stefano; Niazmand, Behrad; Violante, Massimo; Raik, Jaan; Jenihhin, Maksim. (2018). QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. Proceedings of 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS): 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), April 25-27, 2018, Budapest, Hungary. IEEE, 1−6 [ilmumas].
3.1.
2018
Janson, K.; Pihlak, R.; Payandeh Azad, S.; Niazmand, B.; Jervan, G.; Raik, J. (2018). Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers. 2018 16th Biennial Baltic Electronics Conference (BEC): The 16th Biennial Baltic Electronics Conference (BEC), Tallinn, Estonia, 2018. IEEE, 1−4. DOI: 10.1109/BEC.2018.8600989.
3.1.
2018
Janson, K.; Pihlak; R.; Azad, S. P.; Niazmand, B.; Jervan, G.; Raik, J. (2018). AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links. 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, 9-11 July 2018. IEEE, 1−6. DOI: 10.1109/ReCoSoC.2018.8449374.
3.1.
2018
Ghasempouri, T.; Payandeh Azad, S.; Niazmand, B.; Raik, J. (2018). An automatic approach to evaluate assertions' quality based on data-mining metrics. Proceedings: 2nd IEEE International Test Conference in Asia, 15-17 August 2018 Harbin, China: 2nd International Test Conference in Asia (ITC-Asia), Harbin, China, 5-17 August 2018. IEEE, 61−66. DOI: 10.1109/ITC-Asia.2018.00021.
3.1.
2018
Niazmand, B.; Payandeh Azad, S.; Ghasempouri, T.; Raik, J.; Jervan, G. (2018). A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers. In: Proceedings: 2nd IEEE International Test Conference in Asia, 15-17 August 2018 Harbin, China (139−144). 2nd International Test Conference in Asia (ITC-Asia), Harbin, China, 5-17 August 2018: IEEE. DOI: 10.1109/ITC-Asia.2018.00034.
3.1.
2018
Sepúlveda, Johanna; Reinbrecht, Cezar; Payandeh Azad, Siavoosh; Niazmand, Behrad; Jervan, Gert (2018). Understanding MPSoCs: Exploiting Memory Microarchitectural Vulnerabilities of High Performance NoC-Based MPSoCs. 2018 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION (SAMOS XVIII). NEW YORK: ASSOC COMPUTING MACHINERY, 162−166.10.1145/3229631.3239367.
3.1.
2018
Avramenko, Serhiy; Violante, Massim; Payandeh Azad, Siavoosh; Niazmand, Behrad; Jenihhin, Maksim; Raik, Jaan (2018). Upgrading QoSinNoC: Efficient Routing for Mixed Criticality Applications and Power Analysis. 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE: IEEE. DOI: 10.1109/VLSI-SoC.2018.8644866.
3.1.
2018
Hariharan, Ranganathan; Ghasempouri, Tara; Niazmand, Behrad; Raik, Jaan (2018). From RTL Liveness Assertions to Cost-Effective Hardware Checkers. In: Proceedings of 2018 Conference on Design of Circuits and Integrated Systems (DCIS) (1−6). IEEE. DOI: 10.1109/DCIS.2018.8681487.
3.1.
2017
Azad, Siavoosh Payandeh; Niazmand, Behrad; Janson, Karl; Nevin, George; Putkaradze, Tsotne; Oyeniran, Adeboye Stephen; Kaur, Apneet; Raik, Jaan; Jervan, Gert; Ubar, Raimund; Hollstein, Thomas (2017). From Online Fault Detection to Fault Management in Network-on-Chips: A Ground-Up Approach. In: Proc. of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS (1−6). Dresden: IEEE. DOI: 10.1109/DDECS.2017.7934565.
3.1.
2017
Payandeh Azad, Siavoosh; Niazmand, Behrad; Kaur, Apneet; Raik, Jaan; Jervan, Gert; Hollstein, Thomas (2017). Automated area and coverage optimization of minimal latency checkers. 2017 22nd IEEE European Test Symposium (ETS). IEEE. DOI: 10.1109/ETS.2017.7968211.
3.1.
2017
Putkaradze, Tsotne; Payandeh Azad, Siavoosh; Niazmand Behrad; Raik, Jaan; Jervan, Gert; (2017). Fault-Resilient NoC Router with Transparent Resource Allocation. In: Fault-Resilient NoC Router with Transparent Resource Allocation (1−8). 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017): IEEE. DOI: 10.1109/ReCoSoC.2017.8016161.
3.1.
2017
Payandeh Azad, S.; Niazmand, B.; Janson, K.; Kogge, T.; Raik, J.; Jervan, G.; Hollstein, T. (2017). Comprehensive Performance and Robustness Analysis of 2D Turn Models for Network-on-Chips. CONFERENCE PROCEEDINGS (ISCAS 2017): 2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. DOI: 10.1109/ISCAS.2017.8050634.
3.4.
2017
Hariharan, Ranganathan; Niazmand, Behrad; Raik, Jaan (2017). On Fault Detection Efficiency of Reliability Checkers Obtained by Verification Assertion Qualification. In: RESCUE 2017 Workshop on Reliability, Security and Quality ETS17 Fringe Workshop, May 25-26, 2017, Limassol, Cyprus (1−3). European Commission.
3.1.
2016
Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein, (2016). SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints. 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC). IEEE: IEEE Xplore, 1−6. DOI: 10.1109/ReCoSoC.2016.7533903.
3.1.
2016
Niazmand, B.; Azad, S. P.; Flich, J.; Raik, J.; Jervan, G.; Hollstein, T. (2016). Logic-Based Implementation of Fault-Tolerant Routing in 3D Network-on-Chips. 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016), Aug 31-Sep 2, 2016 Nara, Japan: Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) 2016, Nara, Japan, Aug 31-Sep 2, 2016. IEEE: IEEE Xplore, 1−8. DOI: 10.1109/NOCS.2016.7579317.
3.4.
2016
Siavoosh Payandeh Azad; Behrad Niazmand; Jaan Raik; Gert Jervan; Thomas Hollstein (2016). Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems. In: 2nd International Workshop on Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing DREAMCloud 2016 (1−8). arXiv.org: arXiv.
3.1.
2015
Saltarelli, P.; Niazmand, B.; Raik, J.; Hariharan, R.; Govind, V.; Hollstein, T.; Jervan, G. (2015). A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers. 9th International Symposium on Networks-on-Chip (NOCS) 2015. ACM, -. DOI: 10.1145/2786572.2788713.
3.1.
2015
Saltarelli, P.; Niazmand, B.; Hariharan, R.; Raik, J.; Jervan, G.; Hollstein, t. (2015). Automated Minimization of Concurrent Online Checkers for Network-on-Chips. 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015). IEEE, 1−8. DOI: 10.1109/ReCoSoC.2015.7238079.
3.1.
2015
Saltarelli, P.; Niazmand, B.; Raik, J.; Hariharan, R.; Jervan, G.; Holistein, T. (2015). A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. Euromicro Conference on Digital System Design (DSD) 2015. IEEE, 288−292. DOI: 10.1109/DSD.2015.15.
3.1.
2015
Thomas Hollstein; Siavoosh Payandeh Azad; Thilo Kogge; Behrad Niazmand (2015). Mixed-criticality NoC partitioning based on the NoCDepend dependability technique. In: ReCoSoC (1−8). IEEE Xplore.10.1109/ReCoSoC.2015.7238094.
3.2.
2015
Hariharan, Ranganathan; Niazmand, Behrad; Hollstein, Thomas; Raik, Jaan; Jervan, Gert (2015). Extended Checkers for Control Part of Routers in Network-on-Chips. In: MEDIAN Workshop (1−6).
3.4.
2015
Saltarelli, Pietro; Niazmand, Behrad; Hariharan, Ranganathan; Raik, Jaan; Jervan, Gert; Hollstein, Thomas (2015). A Framework for Area-Efficient Concurrent Online Checkers Design. In: MEDIAN2015 Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, November 10-11, 2015, Tallinn, Estonia, 2015 (1−6). EU COST.
3.1.
2014
Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan (2014). Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips. In: Baltic Electronic Conference, Laulasmaa, Estonia (1−4). IEEE.
3.1.
2014
Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan (2014). Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips. In: Baltic Electronic Conference, Laulasmaa, Estonia (1−4). IEEE.
3.1.
2012
Niazmand, Behrad; Reshadi, Midia; Reza, Akram (2012). PathAware: A Contention-aware Selection Function for Application-specific Network-on-Chips. In: NORCHIP, 2012 (1−6).. NORCHIP 2012, Cpenhagen: IEEE.
6.04.2020

Behrad Niazmand

https://www.etis.ee/CV/Behrad_Niazmand/eng
3.12.1986
6202667
55508978
behrad.niazmand@taltech.ee
Research Interests:
• System-on-Chip /Network-on-Chip Design
o Addressing Thermal issues using Adaptive Routing Algorithms
o Working on new Selection Functions
o Distributing Traffic and Temperature using minimal/non-minimal Routing Algorithms
o Extending current Selection Function proposals to Networks with higher dimensions (3D)
o Reconfigurable and Fault-Tolerant Architectures
o Introduction of checkers for Fault Detection in control part of NoC routers
• Computer Architecture
o Studying the Architecture of Multi-Core Processors
• Hardware Modeling and Design
• Computer Networks
• Real-Time Embedded Systems
o Mixed-Criticality Systems

Career

Institutions and positions
07.10.2019–...   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Researcher (0,10)
01.09.2018–07.10.2019   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Researcher (1,00)
01.09.2018–24.12.2018   
Delft University of Technology (TU Delft), Visiting researcher (PostDoc) (1,00)
01.01.2017–31.08.2018   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Junior Researcher (0,75)
06.10.2014–31.12.2016   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Junior Researcher (0,75)
 
 
Education
01.09.2014–16.05.2018   
PhD studies - Dependability Improvements of NoC-based Systems
2010–2012   
M.Sc. in Computer Engineering- Computer Architecture, Science and Research Branch, Islamid Azad University (IAU), Tehran, Iran
2005–2009   
B.Sc. in Computer Hardware Engineering, South Tehran Branch, Islamid Azad University (IAU), Tehran, Iran

Qualifications

Academic degrees
Behrad Niazmand, Doctor's Degree, 2018, (sup) Gert Jervan; Jaan Raik, Dependability Improvements of NoC-based Systems, Tallinn University of Technology School of Information Technologies, Department of Computer Systems.
 
 
Honours & awards
2018, Behrad Niazmand, Accepted as one of the 5 candidates for the semi-final McCluskey PhD thesis award at ETS 2018
2016, Behrad Niazmand, Third Co-supervisor for Master Thesis of Apneet Kaur Sandhu, "Online fault detection methodology for control and data path of IP cores, A case study on Bonfire network-on-chip"
2016, Behrad Niazmand, Second Co-supervisor for Master Thesis of Martin Dída, "Performance Analysis of Bonfire Network on Chip"
2016, Behrad Niazmand, Second Co-supervisor for Master Thesis of Tsotne Putkaradze, "Turn Preserving Fault Tolerance Methodology for On-Chip Routers and Implementation on Bonfire Router"
2016, Behrad Niazmand, Assistance for labs for course "Digital Systems Modeling and Synthesis", code IAY0340, instructor : Professor Peeter Ellervee, Spring Semester.
2015, Behrad Niazmand, • Acquired IT Academy Scholarship (sponsored by Skype) for the second year of PhD studies at Tallinn University of Technology.
2014, Behrad Niazmand, • Acquired Tiger University Scholarship from HITSA for the first year of PhD studies at Tallinn University of Technology.
2010, Behrad Niazmand, • Accepted straightly in Master’s Degree at Islamic Azad University (IAU) – Science and Research Campus without passing the national general university entrance exam(Concours Nationale)
2009, Behrad Niazmand, • Acquired a collaborative invention certificate for "Implementing Ethernet Encryption and Decryption Board based on Microcontrollers", Iran
2009, Behrad Niazmand, • Ranked 1st for three semesters among the Computer engineering Department's Hardware students , IAU, South Tehran branch, Iran
 
 
Fields of research
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.8. Electrical Engineering and Electronics; CERCS CLASSIFICATION: T171 Microelectronics ; SPECIFICATION: Information and Communication Technology (Computer and Systems Engineering) , • System-on-Chip /Network-on-Chip Design o Addressing Thermal issues using Adaptive Routing Algorithms o Working on new Selection Functions o Distributing Traffic and Temperature using minimal/non-minimal Routing Algorithms o Extending current Selection Function proposals to Networks with higher dimensions (3D) o Reconfigurable and Fault-Tolerant Architectures o Introduction of checkers for Fault Detection in control part of NoC routers • Computer Architecture o Studying the Architecture of Multi-Core Processors • Hardware Modeling and Design • Computer Networks • Real-Time Embedded Systems o Mixed-Criticality Systems
 
 
Additional information
• Acceptance of the paper titled “A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers” to Euromicro DSD conference held in Madeira, Portugal, as a co-author.
• Acceptance of the paper titled “Automated Minimization of Concurrent Online Checkers for Networks-on-Chip” 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015) held in Bremen, Germany as a co-author.
• Acceptance of the paper “A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers” in 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2015) held in Vancouver, Canada, as a co-author.
• Acceptance of the paper “Mixed-Criticality MPSoC Partitioning based on the NoCDepend Dependability Technique” in 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015) held in Bremen, Germany, as a co-author.
• “Extended Checkers for Control Part of Routers in Network-on-Chips”, MEDIAN 2015, Manufacturable and Dependable Multicore Architectures at Nanoscale, DATE Friday Workshop, March 13, 2015, Grenoble, France
• “Extended Checkers for Control Part of Routers in Network-on-Chips”, Info- ja kommunikatsioonitehnoloogia doktorikool (IKTDK) 2014 conference for Doctoral Students in ICT, December 5-6, Rakvere, Estonia.
• "Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips”, 14th Biennial Baltic Electronics Conference (BEC), October 6-8, 2014, Laulasmaa, Estonia.
• Seminar in department of Computer Engineering at Tallinn University of Technology, for practicing for BEC conference
• "Initialization and Installation of DHCP Service in windows Server 2003" Delivered as a term paper for the Computer Networks Lab. at Computer Engineering Department of IAU, 2009.
• "N-way Set-Associative Cache", Delivered as a term paper for Computer architecture Course, Under the supervision of
Dr. A. Broumandnia, at Computer Engineering Department of IAU, 2008.
• "Error Detection and Correction" Delivered as a term paper for Signals and Systems course, Under the supervision of
Dr. A. Broumandnia, at Computer Engineering Department of IAU, 2008.
• “Clock with AVR Microcontroller" Delivered as a course project for Microprocessor II course, under the supervision of
Dr. M. Kazemi Parsa, at Computer Engineering Department of IAU, 2009.

Projects in progress

Completed projects

Supervised dissertations

Publications

Category
Year
Publication
 
3.1.
2020
Reinbrecht, Cezar; Hamdioui, Said; Taouil, Mottaqiallah; Niazmand, Behrad; Ghasempouri, Tara; Raik, Jaan; Sepúlveda, Johanna; (2020). LiD-CAT: A Lightweight Detector for Cache Attacks. In: European Test Symposium (ETS) 2020 (Ed.). LiD-CAT: A Lightweight Detector for Cache Attacks. IEEE [forthcoming].
3.1.
2019
Niazmand, Behrad; Payandeh Azad, Siavoosh; Jervan, Gert; Sepúlveda, Johanna; (2019). Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks. In: Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks (672−676). IEEE: IEEE. DOI: 10.1109/DSD.2019.00108.
3.5.
2019
Niazmand, Behrad; Reinbrecht, Cezar; Raik, Jaan; Jervan, Gert; Sepulveda, Johanna (2019). Towards Formal Verification of Cache Access-based Side-Channel Attacks. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, TUZ 2019. Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, TUZ 2019, 1−2.
2.3.
2018
Niazmand, B. (2018). Dependability Improvements of NoC-based Systems. (Doktoritöö, Tallinn University of Technology). TTÜ Press: TTU Press.
3.1.
2018
Avramenko, Serhiy; Azad, Siavoosh Payandeh; Esposito, Stefano; Niazmand, Behrad; Violante, Massimo; Raik, Jaan; Jenihhin, Maksim. (2018). QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. Proceedings of 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS): 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), April 25-27, 2018, Budapest, Hungary. IEEE, 1−6 [forthcoming].
3.1.
2018
Janson, K.; Pihlak, R.; Payandeh Azad, S.; Niazmand, B.; Jervan, G.; Raik, J. (2018). Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers. 2018 16th Biennial Baltic Electronics Conference (BEC): The 16th Biennial Baltic Electronics Conference (BEC), Tallinn, Estonia, 2018. IEEE, 1−4. DOI: 10.1109/BEC.2018.8600989.
3.1.
2018
Janson, K.; Pihlak; R.; Azad, S. P.; Niazmand, B.; Jervan, G.; Raik, J. (2018). AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links. 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, 9-11 July 2018. IEEE, 1−6. DOI: 10.1109/ReCoSoC.2018.8449374.
3.1.
2018
Ghasempouri, T.; Payandeh Azad, S.; Niazmand, B.; Raik, J. (2018). An automatic approach to evaluate assertions' quality based on data-mining metrics. Proceedings: 2nd IEEE International Test Conference in Asia, 15-17 August 2018 Harbin, China: 2nd International Test Conference in Asia (ITC-Asia), Harbin, China, 5-17 August 2018. IEEE, 61−66. DOI: 10.1109/ITC-Asia.2018.00021.
3.1.
2018
Niazmand, B.; Payandeh Azad, S.; Ghasempouri, T.; Raik, J.; Jervan, G. (2018). A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers. In: Proceedings: 2nd IEEE International Test Conference in Asia, 15-17 August 2018 Harbin, China (139−144). 2nd International Test Conference in Asia (ITC-Asia), Harbin, China, 5-17 August 2018: IEEE. DOI: 10.1109/ITC-Asia.2018.00034.
3.1.
2018
Sepúlveda, Johanna; Reinbrecht, Cezar; Payandeh Azad, Siavoosh; Niazmand, Behrad; Jervan, Gert (2018). Understanding MPSoCs: Exploiting Memory Microarchitectural Vulnerabilities of High Performance NoC-Based MPSoCs. 2018 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION (SAMOS XVIII). NEW YORK: ASSOC COMPUTING MACHINERY, 162−166.10.1145/3229631.3239367.
3.1.
2018
Avramenko, Serhiy; Violante, Massim; Payandeh Azad, Siavoosh; Niazmand, Behrad; Jenihhin, Maksim; Raik, Jaan (2018). Upgrading QoSinNoC: Efficient Routing for Mixed Criticality Applications and Power Analysis. 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE: IEEE. DOI: 10.1109/VLSI-SoC.2018.8644866.
3.1.
2018
Hariharan, Ranganathan; Ghasempouri, Tara; Niazmand, Behrad; Raik, Jaan (2018). From RTL Liveness Assertions to Cost-Effective Hardware Checkers. In: Proceedings of 2018 Conference on Design of Circuits and Integrated Systems (DCIS) (1−6). IEEE. DOI: 10.1109/DCIS.2018.8681487.
3.1.
2017
Azad, Siavoosh Payandeh; Niazmand, Behrad; Janson, Karl; Nevin, George; Putkaradze, Tsotne; Oyeniran, Adeboye Stephen; Kaur, Apneet; Raik, Jaan; Jervan, Gert; Ubar, Raimund; Hollstein, Thomas (2017). From Online Fault Detection to Fault Management in Network-on-Chips: A Ground-Up Approach. In: Proc. of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS (1−6). Dresden: IEEE. DOI: 10.1109/DDECS.2017.7934565.
3.1.
2017
Payandeh Azad, Siavoosh; Niazmand, Behrad; Kaur, Apneet; Raik, Jaan; Jervan, Gert; Hollstein, Thomas (2017). Automated area and coverage optimization of minimal latency checkers. 2017 22nd IEEE European Test Symposium (ETS). IEEE. DOI: 10.1109/ETS.2017.7968211.
3.1.
2017
Putkaradze, Tsotne; Payandeh Azad, Siavoosh; Niazmand Behrad; Raik, Jaan; Jervan, Gert; (2017). Fault-Resilient NoC Router with Transparent Resource Allocation. In: Fault-Resilient NoC Router with Transparent Resource Allocation (1−8). 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017): IEEE. DOI: 10.1109/ReCoSoC.2017.8016161.
3.1.
2017
Payandeh Azad, S.; Niazmand, B.; Janson, K.; Kogge, T.; Raik, J.; Jervan, G.; Hollstein, T. (2017). Comprehensive Performance and Robustness Analysis of 2D Turn Models for Network-on-Chips. CONFERENCE PROCEEDINGS (ISCAS 2017): 2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. DOI: 10.1109/ISCAS.2017.8050634.
3.4.
2017
Hariharan, Ranganathan; Niazmand, Behrad; Raik, Jaan (2017). On Fault Detection Efficiency of Reliability Checkers Obtained by Verification Assertion Qualification. In: RESCUE 2017 Workshop on Reliability, Security and Quality ETS17 Fringe Workshop, May 25-26, 2017, Limassol, Cyprus (1−3). European Commission.
3.1.
2016
Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein, (2016). SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints. 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC). IEEE: IEEE Xplore, 1−6. DOI: 10.1109/ReCoSoC.2016.7533903.
3.1.
2016
Niazmand, B.; Azad, S. P.; Flich, J.; Raik, J.; Jervan, G.; Hollstein, T. (2016). Logic-Based Implementation of Fault-Tolerant Routing in 3D Network-on-Chips. 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016), Aug 31-Sep 2, 2016 Nara, Japan: Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) 2016, Nara, Japan, Aug 31-Sep 2, 2016. IEEE: IEEE Xplore, 1−8. DOI: 10.1109/NOCS.2016.7579317.
3.4.
2016
Siavoosh Payandeh Azad; Behrad Niazmand; Jaan Raik; Gert Jervan; Thomas Hollstein (2016). Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems. In: 2nd International Workshop on Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing DREAMCloud 2016 (1−8). arXiv.org: arXiv.
3.1.
2015
Saltarelli, P.; Niazmand, B.; Raik, J.; Hariharan, R.; Govind, V.; Hollstein, T.; Jervan, G. (2015). A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers. 9th International Symposium on Networks-on-Chip (NOCS) 2015. ACM, -. DOI: 10.1145/2786572.2788713.
3.1.
2015
Saltarelli, P.; Niazmand, B.; Hariharan, R.; Raik, J.; Jervan, G.; Hollstein, t. (2015). Automated Minimization of Concurrent Online Checkers for Network-on-Chips. 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015). IEEE, 1−8. DOI: 10.1109/ReCoSoC.2015.7238079.
3.1.
2015
Saltarelli, P.; Niazmand, B.; Raik, J.; Hariharan, R.; Jervan, G.; Holistein, T. (2015). A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. Euromicro Conference on Digital System Design (DSD) 2015. IEEE, 288−292. DOI: 10.1109/DSD.2015.15.
3.1.
2015
Thomas Hollstein; Siavoosh Payandeh Azad; Thilo Kogge; Behrad Niazmand (2015). Mixed-criticality NoC partitioning based on the NoCDepend dependability technique. In: ReCoSoC (1−8). IEEE Xplore.10.1109/ReCoSoC.2015.7238094.
3.2.
2015
Hariharan, Ranganathan; Niazmand, Behrad; Hollstein, Thomas; Raik, Jaan; Jervan, Gert (2015). Extended Checkers for Control Part of Routers in Network-on-Chips. In: MEDIAN Workshop (1−6).
3.4.
2015
Saltarelli, Pietro; Niazmand, Behrad; Hariharan, Ranganathan; Raik, Jaan; Jervan, Gert; Hollstein, Thomas (2015). A Framework for Area-Efficient Concurrent Online Checkers Design. In: MEDIAN2015 Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, November 10-11, 2015, Tallinn, Estonia, 2015 (1−6). EU COST.
3.1.
2014
Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan (2014). Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips. In: Baltic Electronic Conference, Laulasmaa, Estonia (1−4). IEEE.
3.1.
2014
Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan (2014). Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips. In: Baltic Electronic Conference, Laulasmaa, Estonia (1−4). IEEE.
3.1.
2012
Niazmand, Behrad; Reshadi, Midia; Reza, Akram (2012). PathAware: A Contention-aware Selection Function for Application-specific Network-on-Chips. In: NORCHIP, 2012 (1−6).. NORCHIP 2012, Cpenhagen: IEEE.
6.04.2020

Otsi projekti

  • {{item.Name}}
Asutus on projekti finantseerija   Asutus on projekti teostaja  
  • {{searchListItem.Name}}
Kõik   Tavaprojektid   Ülemprojektid   Alamprojektid  
Uus Frascati (2015)
Uus ja vana Frascati (otsing uue järgi väljastab ka seotud vanad)
Kõik
Käimasolevad
Lõppenud
Algus
Hajus
Täpne
Lihtotsing Tühjenda
  • Leitud 3 kirjet
ProgrammLiikNumberNimiProjekti algusProjekti lõppVastutav täitjaAsutusFinantseerijapoolne rahastamine
MUUVFP15002EL Horizon 2020 uurimisprojekt IMMORTAL01.03.201528.02.2018Jaan RaikTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 377 750,00 EUR
TKAlamprojektTAR16013 (EXCITE) (TK148)IT Tippkeskus EXCITE01.09.201601.03.2023Maarja KruusmaaTallinna Tehnikaülikool, Infotehnoloogia teaduskond, Biorobootika keskus; Cybernetica AS2 121 014,65 EUR
IUTIUT19-1Usaldusväärsed mitmetuumalised arvutisüsteemid01.01.201431.12.2019Jaan RaikTallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut1 572 000,00 EUR