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Karl Janson

https://www.etis.ee/CV/Karl_Janson/est
karl.janson@taltech.ee
O-2494-2016

Teenistuskäik

Töökohad ja ametid
01.09.2019–...   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, insener (0,50)
01.01.2019–31.08.2019   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, doktorant-nooremteadur (0,50)
01.10.2018–31.12.2018   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, doktorant-nooremteadur (1,00)
01.09.2017–30.09.2018   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, doktorant-nooremteadur (0,50)
01.01.2017–31.08.2017   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, Nooremteadur (0,50)
01.09.2016–31.12.2016   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Nooremteadur (0,50)
01.09.2015–31.08.2016   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Nooremteadur (0,25)
 
 
Haridustee
2015–2021   
Ph.D. - Robustse marsruutimise, side ja arvutuse tehnikad mitmeprotsessorilistes süsteemides
2013–2015   
M.Sc. - Tallinna Tehnikaülikool (TTÜ). Eriala: Arvutisüsteemid
2009–2013   
B.Sc. - Tallinna Tehnikaülikool (TTÜ). Eriala: Arvutisüsteemid
 
 
Teadusorganisatsiooniline ja -administratiivne tegevus
2016−2017   
IEEE Eesti tudengiharu hariduslike ürituste korraldamine

Kvalifikatsioon

Teaduskraadid
Karl Janson, doktorikraad, 2021, (juh) Thomas Hollstein; Jaan Raik, Techniques for Robust Routing, Communication and Computation in Multiprocessor Systems (Robustse marsruutimise, side ja arvutuse tehnikad mitmeprotsessorilistes süsteemides), Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut
Karl Janson, magistrikraad, 2015, (juh) Muhammad Adeel Tajammul, Implementation of HEVC Computational Kernels on DRRA (HEVC arvutuslike tuumade implementeerimine DRRA-l), Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool.
 
 
Teadustöö põhisuunad
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.6. Arvutiteadused; CERCS KLASSIFIKAATOR: T120 Süsteemitehnoloogia, arvutitehnoloogia; TÄPSUSTUS: Küberfüüsikaliste süsteemine veakindlus

Lõppenud projektid

Juhendatud väitekirjad

Publikatsioonid

Klass
Aasta
Publikatsioon
 
3.1.
2019
Malburg, J.; Janson, K.; Raik, J.; Dannemann, F. (2019). Fault-aware Performance Assessment Approach for Embedded Networks. 2019 IEEE 22st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS): 22ndIEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019), Cluj-Napoca, Rumeenia, 24.04.2019 - 26.04.2019. IEEE, 1−4.
3.1.
2018
Janson, Karl; Treudler, Carl Johann; Hollstein, Thomas; Raik, Jaan; Jenihhin, Maksim; Fey, Goerschwin (2018). Software-Level TMR Approach for On-Board Data Processing in Space Applications. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS): 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), April 25-27, 2018, Budapest, Hungary. IEEE, 1−6. DOI: 10.1109/DDECS.2018.00033.
3.1.
2018
Janson, K.; Pihlak, R.; Payandeh Azad, S.; Niazmand, B.; Jervan, G.; Raik, J. (2018). Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers. 2018 16th Biennial Baltic Electronics Conference (BEC): The 16th Biennial Baltic Electronics Conference (BEC), Tallinn, Estonia, 2018. IEEE, 1−4. DOI: 10.1109/BEC.2018.8600989.
3.1.
2018
Janson, K.; Pihlak; R.; Azad, S. P.; Niazmand, B.; Jervan, G.; Raik, J. (2018). AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links. 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, 9-11 July 2018. IEEE, 1−6. DOI: 10.1109/ReCoSoC.2018.8449374.
3.1.
2017
Azad, Siavoosh Payandeh; Niazmand, Behrad; Janson, Karl; Nevin, George; Putkaradze, Tsotne; Oyeniran, Adeboye Stephen; Kaur, Apneet; Raik, Jaan; Jervan, Gert; Ubar, Raimund; Hollstein, Thomas (2017). From Online Fault Detection to Fault Management in Network-on-Chips: A Ground-Up Approach. In: Proc. of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS (1−6). Dresden: IEEE. DOI: 10.1109/DDECS.2017.7934565.
3.1.
2017
Payandeh Azad, S.; Niazmand, B.; Janson, K.; Kogge, T.; Raik, J.; Jervan, G.; Hollstein, T. (2017). Comprehensive Performance and Robustness Analysis of 2D Turn Models for Network-on-Chips. CONFERENCE PROCEEDINGS (ISCAS 2017): 2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. DOI: 10.1109/ISCAS.2017.8050634.
17.01.2021

Karl Janson

https://www.etis.ee/CV/Karl_Janson/eng
karl.janson@taltech.ee
O-2494-2016

Career

Institutions and positions
01.09.2019–...   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Engineer (0,50)
01.01.2019–31.08.2019   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Early Stage Researcher (0,50)
01.10.2018–31.12.2018   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Junior Researcher (1,00)
01.09.2017–30.09.2018   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Early Stage Researcher (0,50)
01.01.2017–31.08.2017   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Junior Researcher (0,50)
01.09.2016–31.12.2016   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Junior Researcher (0,50)
01.09.2015–31.08.2016   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Junior Researcher (0,25)
 
 
Education
2015–2021   
Ph.D. - Techniques for Robust Routing, Communication and Computation in Multiprocessor Systems
2013–2015   
M.Sc. - Tallinn University of Technology (TUT). Speciality: Computer and Systems Engineering
2009–2013   
B.Sc. - Tallinn University of Technology (TUT). Speciality: Computer and Systems Engineering
 
 
R&D related managerial and administrative work
2016−2017   
Organizing of educational IEEE Estonia student branch events

Qualifications

Academic degrees
Karl Janson, Doctor's Degree, 2021, (sup) Thomas Hollstein; Jaan Raik, Techniques for Robust Routing, Communication and Computation in Multiprocessor Systems, Tallinn University of Technology School of Information Technologies, Department of Computer Systems
Karl Janson, Master's Degree, 2015, (sup) Muhammad Adeel Tajammul, Implementation of HEVC Computational Kernels on DRRA, Tallinn University of Technology School of Information Technologies, Department of Computer Engineering Chair of Computer Systems Design.
 
 
Fields of research
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.6. Computer Sciences; CERCS CLASSIFICATION: T120 Systems engineering, computer technology ; SPECIFICATION: Fault tolerance of cyberphysical systems
 
 

Completed projects

Supervised dissertations

Publications

Category
Year
Publication
 
3.1.
2019
Malburg, J.; Janson, K.; Raik, J.; Dannemann, F. (2019). Fault-aware Performance Assessment Approach for Embedded Networks. 2019 IEEE 22st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS): 22ndIEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019), Cluj-Napoca, Rumeenia, 24.04.2019 - 26.04.2019. IEEE, 1−4.
3.1.
2018
Janson, Karl; Treudler, Carl Johann; Hollstein, Thomas; Raik, Jaan; Jenihhin, Maksim; Fey, Goerschwin (2018). Software-Level TMR Approach for On-Board Data Processing in Space Applications. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS): 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), April 25-27, 2018, Budapest, Hungary. IEEE, 1−6. DOI: 10.1109/DDECS.2018.00033.
3.1.
2018
Janson, K.; Pihlak, R.; Payandeh Azad, S.; Niazmand, B.; Jervan, G.; Raik, J. (2018). Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers. 2018 16th Biennial Baltic Electronics Conference (BEC): The 16th Biennial Baltic Electronics Conference (BEC), Tallinn, Estonia, 2018. IEEE, 1−4. DOI: 10.1109/BEC.2018.8600989.
3.1.
2018
Janson, K.; Pihlak; R.; Azad, S. P.; Niazmand, B.; Jervan, G.; Raik, J. (2018). AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links. 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, 9-11 July 2018. IEEE, 1−6. DOI: 10.1109/ReCoSoC.2018.8449374.
3.1.
2017
Azad, Siavoosh Payandeh; Niazmand, Behrad; Janson, Karl; Nevin, George; Putkaradze, Tsotne; Oyeniran, Adeboye Stephen; Kaur, Apneet; Raik, Jaan; Jervan, Gert; Ubar, Raimund; Hollstein, Thomas (2017). From Online Fault Detection to Fault Management in Network-on-Chips: A Ground-Up Approach. In: Proc. of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS (1−6). Dresden: IEEE. DOI: 10.1109/DDECS.2017.7934565.
3.1.
2017
Payandeh Azad, S.; Niazmand, B.; Janson, K.; Kogge, T.; Raik, J.; Jervan, G.; Hollstein, T. (2017). Comprehensive Performance and Robustness Analysis of 2D Turn Models for Network-on-Chips. CONFERENCE PROCEEDINGS (ISCAS 2017): 2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. DOI: 10.1109/ISCAS.2017.8050634.
17.01.2021

Otsi projekti

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Kõik   Tavaprojektid   Ülemprojektid   Alamprojektid  
Uus Frascati (2015)
Uus ja vana Frascati (otsing uue järgi väljastab ka seotud vanad)
Kõik
Käimasolevad
Lõppenud
Algus
Hajus
Täpne
Lihtotsing Tühjenda
  • Leitud 1 kirjet
ProgrammLiikNumberNimiProjekti algusProjekti lõppVastutav täitjaAsutusFinantseerijapoolne rahastamine
IUTIUT19-1Usaldusväärsed mitmetuumalised arvutisüsteemid01.01.201431.12.2019Jaan RaikTallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut1 572 000,00 EUR