See veebileht kasutab küpsiseid kasutaja sessiooni andmete hoidmiseks. Veebilehe kasutamisega nõustute ETISe kasutustingimustega. Loe rohkem
Olen nõus

Marina Brik

https://www.etis.ee/CV/Marina_Brik/est
marina.brik@ttu.ee

Teenistuskäik

Töökohad ja ametid
01.01.2010–31.12.2011   
ELIKO TAK (Eliko Tehnoloogia Arenduskeskus OÜ) Sep.2010-Jan.2011
01.09.2001–31.08.2016   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool , Teadur (1,00)
 
 
Haridustee
2000–2003   
EKA RKK, graafiline disain
1995–2002   
tehnikateaduste doktor
 
 
Lisainfo
Bakalaureuseõppe õppeainete praktiliste tööde juhendaja:

- IAF0041 Arvutid (kuni 2012 a. (kaasaarvatud))

2010 a. - 124 tudengit
2011 a. - 75 tudengit
2012 a. - 70 tudengit

- IAG0581 Programmeerimine I

2010 a. - 33 tudengit
2011 a. - 21 tudengit
2012 a. - 46 tudengit
2013 a. - 43 tudengit
2014 a. - 36 tudengit
2015 a. - 70 tudengit
- IAG0582 Programmeerimine II

2013 a. - 28 tudengit
2014 a. - 26 tudengit
2015 a. - 32 tudengit
2016 a. - 40 tudengit
- IAG0090 Algoritmid ja andmestruktuurid

2011 a. - 40 tudengit
2012 a. - 39 tudengit
2013 a. - 24 tudengit
2014 a. - ~ 40 tudengit
2015 a. - ~ 40 tudengit
- IXX1410 Tarkvara - projekt
2016 a. - 10 tudengit
Bakalaureuseõpe lõputööde juhendamine:

Aastail 2006-2011 13 juhendatavat,
aastail 2012-2013 3 juhendatavat,
Kevad 2014- 1 juhendatav.

Õppemetoodiline töö ja sellega seotud arendustegevus:

- õppeainete „Arvutid“(2012 a.) praktikumide materjalide koostamine ja täiendamine; õppeainete „Tarkvara projekt“ praktikumide materjalide koostamine ja täiendamine; „Programmeerimine I“, „Programmeerimine II" praktikumide materjalide koostamine inglise keeles;
- õppeainete „Algoritmid ja andmestruktuurid“ praktikumide materjalide tõlkimine eesti keelest vene keelde (täiendamine);
- arvuti- ja süsteemitehnika õppesuuna bakalaureuseõppe ja magistriõppe lõpetajate lõputööde kaitsmiskomisjoni liige.

Kvalifikatsioon

Teaduskraadid
Marina Brik, doktorikraad, 2002, (juh) Raimund Ubar, Digitaalsüsteemide juhtseadmete testide genereerimise meetodite uurimine ja väljatöötamine, 2002., Tallinna Tehnikaülikool, Infotehnoloogia teaduskond.
Marina Brik, magistrikraad (teaduskraad), 1994, (juh) Raimund Ubar, Mitmetastmeline testide generaator lõplike automaatide jaoks, 1994., Tallinna Tehnikaülikool, Infotehnoloogia teaduskond.
 
 
Lisainfo

Enesetäiendused:


Feb 2010 TTÜ - Prof. Erik Larsson(Linköpingi ülikool). Checking distributed properties to detect interconnect latency
post-doc Urban Ingelsson(Linköpingi ülikool). Investigation into voltage and variation-aware manufacturing test

veebruar 2010 TTÜ Linköpingi ülikooli Prof. Zebo Pengi külalisloeng:
Challenges and Solutions for the Design of Fault-Tolerant Systems


jaanaar 2010 - MOC-6292 Installing and Configuring Windows 7 Client
Windows 7 kasutajakursus
Tunnistus nr. 23949
IT koolitus


Enesetäiendus 2011:

June 2011 TTÜ - CREDES Summer School "Dependable Systems Design"
Feb 2011 TUT DCE - "High Level Synthesis of Digital Systems" prof. Samary Baranov (Bar Ilan University/School of Engineering, Ramat Gan, Israel)

Enesetäiendus 2012:

jaanuar 2012 TTÜ - CREDES koolitus "HW System-Level Design and Modeling ESL Using C/C++, SystemC and TLM-2.0" prof. Zainalabedin Navabi (Worcester Polytechnic Institute, USA; University of Tehran, Iran)

Enesetäiendus 2013:

RTL Design and Test with HDLs. Comprehensive FPGA and ASIC design course in two parts
11-14 veebruar, 2013
Prof. Zainalabedin Navabi (Worcester Polytechnic Institute, USA; University of Tehran, Iran)

Enesetäiendus 2014:

IT standardimise teemaline seminar
24. jaanuar 2014
Taavi Valdlo

Erinevate ENETA loengute ja konverentside külastamine (Microsoft Corporation)

ATI, CEBE seminarid
s.h.
4. detsember 2014 “Dealing with Physical Issues in Many-Cores” Prof. Zainalabedin Navabi, Worcester Polytechnic Institute, USA / University of Tehran, Iran

14. jaanuar,2016 "Wireless Communication for Industrial Control: Test and Dependability for the Baseband-Processor" Prof. H.T. Vierhaus
10.-11. november 2015 "MEDIAN Finale" workshop, Tallinn

Publikatsioonid

Klass
Aasta
Publikatsioon
 
1.1.
2014
Jasnetski, Artjom; Ubar, Raimund; Tsertov, Anton; Brik, Marina (2014). Software-based self-test generation for microprocessors with high-level decision diagrams. Proceedings of the Estonian Academy of Sciences, 63 (1), 48−61.
3.1.
2014
Ubar, Raimund; Tsertov, Anton; Jasnetski, Artjokm; Brik, Marina. (2014). Software-based Self-Test Generation for Microprocessors with High-Level Decision Diagrams. Fortaleza, Brazil: IEEE Computer Society.
3.1.
2014
Kruus, Helena; Brik, Marina; Kruus, Margus; Ruberg, Priit; Viies, Vladimir; Ellervee, Peeter. (2014). Hardware Close Programming for Freshmen. Microelectronics Education (EWME), 10th European Workshop on : IEEE, 93−96.10.1109/EWME.2014.6877403.
3.1.
2012
Kruus, H.; Ubar, R.; Ellervee, P.; Gorev, M.; Pesonen, V.; Devadze, S.; Orasson, E.; Brik, M.; Min, M.; Annus, P.; Kruus, M.; Meigas, K. (2012). A Benchmark Suite for Evaluating the Efficiency of Test Tools. BEC 2012 : 13th biennial Baltic Electronics Conference : proceedings of the 13th biennial Baltic Electronics Conference : Tallinn University of Technology, October 3-5, 2012, Tallinn, Estonia. Tallinn, 2012: The 13th Biennial Baltic Electronics Conference (BEC2012). Tallinn University of Technology, 85−88.
3.2.
2012
Ubar, Raimund; Kostin, Sergei; Orasson, Elmet; Evartson, Teet; Brik, Marina (2012). A Tool for Teaching Hierarchical Fault Diagnosis in Digital Circuits. Proc. of 9th European Workshop on Microelectronics Education – EWME’12. Grenoble, France: CNRS, 1−4.
1.2.
2011
Kostin, Sergei; Ubar, Raimund; Raik, Jaan; Brik, Marina (2011). Hierarchical Physical Defect Reasoning in Digital Circuits. Estonian Journal of Engineering, 17 (3), 1−15.
3.1.
2009
Kostin, Sergei; Ubar, Raimund; Raik, Jaan; Aarna, Margit; Brik, Marina; Wuttke, Heinz-Dietrich (2009). Teaching Research in the Laboratory Using Diagnosis Environment for Digital Systems. 20th EAEEIE Conference Formal Proceedings: 20th EAEEIE Annual Conference on Innovation in Education for Electrical and Information Engineering, Valencia, Spain, June 22-24, 2009. IEEE, 1−4. DOI: 10.1109/EAEEIE.2009.5335462.
3.1.
2008
Ubar, Raimund; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Brik, Marina; Instenberg, Martin; Wuttke, Heinz-Dieter (2008). Diagnostic Modeling of Microprocessors with High-Level Decision Diagrams. In: 11th Biennial Baltic Electronics Conference (147−150). . IEEE.
3.1.
2006
Ubar, Raimund; Brik, Marina; Jutman, Artur; Raik, Jaan; Bengtsson, Tomas; Kumar, Shashi (2006). Functional Test Generation for Finite State Machines. Proceedings of the Baltic Electronics Conference: Baltic Electronics Conference, Laulasmaa, oktoober 2006. IEEE, 205−208.
3.4.
2006
Robal, T.;Brik, M.; Aarna, M. (2006). e-Learning of Digital Logic. Using e-Environments in Teaching Digital Logic. EWME 2006 Proceedings: 6th International Workshop on Microelectronics Education. Ed. L-R Zheng, J. Nurmi, J. Liu, R.Weerasekera, H. Tenhunen. Stockholm, Sweden: Royal Institue of Technology KTH, 120−123.
3.4.
2005
Brik, M.; Fomina, E.; Ubar, R. (2005). A Proposal for Optimization of Low-Powered FSM Testing. Proceedings of the East West Design Test Workshop (IEEE EWDTW’05) (15−20).. Odessa: EWDTW.
3.4.
2005
Fomina, E.; Vassilyev, R.; Brik, M. (2005). A New Approach to State Encoding of Low Power FSM. Proc. of the East West Design Test Workshop. Odessa: EWDTW, 21−26.
3.1.
2004
Brik, Marina; Raik, Jaan; Ubar, Raimund; Ivask, Eero (2004). On using genetic algorithm for test generation. 9th Biennial Baltic Electronics Conference. , 233−236.
3.2.
2004
Ubar, Raimund-Johannes; Aarna, Margit; Brik, Marina; Raik, Jaan (2004). High level fault modeling in digital systems. In: Shaker Verlag (486−491). . Aachen: Shaker Verlag.
3.4.
2004
Brik, M.; Raik, J.; Ubar, R.; Ivask, E. (2004). GA-based Test Generation for sequential circuits. Proc. of East-West Design&Test Workshop(EWDTW'04): Ukraine, September 23-26, 2004. , 30−34.
3.4.
2004
Ubar, R.; Aarna, M.; Brik, M.; Evartson, T.; Raik, J. (2004). High Level Fault Models for Digital Systems. University Research, Industry, International Cooperation: Minsk. Minsk, 303−310.
1.2.
2002
Ubar, R.; Raik, J.; Ivask, E.; Brik, M. (2002). Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta universitatis - series Electronics and Energetics, 15 (1), 123−136.
2.3.
2002
Brik, M. (2002). Investigation and Development of Test Generation Methods for Control Part of Digital Systems. (Doktoritöö, Tallinna Tehnikaülikool). Tallinn: Tallinn Technical University Press.
3.1.
2002
Ubar, R.; Raik, J.; Ivask, E.; Brik, M. (2002). Mixed-level defect simulation in data-paths of digital systems, Microelectronics. MIEL 2002. 23rd International Conference, 2: 12-15 May 2002. IEEE Computer Society Press, 617−620.
3.1.
2002
Ubar, Raimund; Raik, Jaan; Ivask, Eero; Brik, Marina (2002). Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. Proceedings of the IEEE Workshop on Electronic Design, Test and Applications – DELTA’02: Christchurch, New Zealand, 29-31 January 2002. IEEE Computer Society Press, 86−91.
3.4.
2002
Ubar, R.; Raik, J.; Ivask, E.; Brik, M. (2002). Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the International Conference on Computer Dependability: Tomsk, Russia, September 10-13, 2002. , 315−319.
3.4.
2001
Ubar, R.; Raik, J.; Ivask, E.; Brik, M. (2001). Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 2: 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2001. , 617−620.
3.4.
2000
Brik, Marina; Raik, Jaan; Ubar, Raimund (2000). Hierarchical fault simulation for finite state machines. 7th Baltic Electronics Conference, Tallinn, October 8-11. , 145−148.
3.4.
2000
Ubar, R.; Brik, M. (2000). Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems: Gdynia (Poland), June 15-17, 2000. 533−538.
3.4.
1999
Brik, M.; Ubar, R. (1999). Two-Level Simulation-Based Test Generation for Finite State Machines. IEEE 17th NORCHIP Conference, Oslo, Nov. 8-9, 1999. 211−216.
3.1.
1998
Brik, Marina; Jervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund (1998). Hierarchical Test Generation for Digital Systems. Mixed Design of Integrated Circuits and Systems (131−136). . Kluwer Academic Publishers.
3.4.
1998
Brik, M.; Ubar, R. (1998). An improved test generation approach for sequential circuits using decision diagrams. 6th Biennial Conference on Electronics and Microsystems Technology: Tallinn, 1998. 155−158.
1.2.
1997
Brik, Marina; Jervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund (1997). Mixed-Level Test Generator for Digital Systems. Proceedings of the Estonian Academy of Sciences. Engineering, 3 (4), 271−282.
3.4.
1997
Brik, M.; Jervan, G.; Markus, A.; Raik, J.; Ubar, R. (1997). A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. 4-th International Workshop on Computer Aided Design of Modern Devices and ICs., Poznan, Poland, June 12-14, 1997. , 415−420.
3.1.
1996
Ubar, R.; Brik, M. (1996). Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. Lecture Notes in Computer Science No 1150. Dependable Computing - EDCC-2 (268−281).. Springer Verlag.
3.4.
1996
Ubar, R.; Brik, M. (1996). Test generation for finite state machines. BEC '96. The 5th Biennial Baltic Electronics Conference. Proceedings (233−236).. Tallinn: Tallinn Technical University.
3.4.
1994
"Dušshina, Julia;Brik, Marina" (1994). Test generation for control faults in digital systems. 1: BEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia).. Tallinn: Tallinna Tehnikaülikool, 325−330.
3.4.
1994
"Brik, Marina;Ubar, Raimund-Johannes" (1994). Hierarchical test generation for finite state machines. 1: BEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia).. Tallinn, 319−324.
7.01.2019

Marina Brik

https://www.etis.ee/CV/Marina_Brik/eng
marina.brik@ttu.ee

Career

Institutions and positions
01.01.2010–31.12.2011   
Competence Centre in Electronics-, Info- and Communication Technologies ELIKO Sep.2010-Jan.2011
01.09.2001–31.08.2016   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Test and Verification, Researcher (1,00)
 
 
Education
2000–2003   
EAA, graphical design
1995–2002   
D.Sc/PhD (TUT)
 
 
Additional information
Supervisor of practical lessons in bachelor's subjects:

- IAF0041 Computers (right up to 2012 (incl.))

2010 - 124 students
2011 - 75 students
2012 - 70 students

- IAG0581 Programming I

2010 - 33 students
2011 - 21 students
2012 - 46 students
2013 - 43 students
2014 - 36 students
2015 - 70 students
- IAG0582 Programming II

2013 - 28 students
2014 - 26 students
2015 - 32 students
2016 - 40 students

- IAG0090 Algorithms and Data Structures

2011 - 40 students
2012 - 39 students
2013 - 24 students
2014 - ~ 40 students
2015 - ~ 40 students

- IXX1410 Software - project
2016 - 10 students
Supervision of Bachelor Theses:

Years 2006-2011: 13 graduates.
years 20012-2013 3 graduates.
Spring 2014 (according to plan) - 1 graduate.

Methodological work and related activities:

- Preparation and upgrading of practical materials for the courses: Computers(2012), Software project, Programming I (English), Programming II (English).
- Translation of practical materials from Estonian into Russian for the course (supplement): Algorithms and Data Structures
- Defense committee member of computer and system engineering bachelor's and master's theses.

Qualifications

Academic degrees
Marina Brik, Doctor's Degree, 2002, (sup) Raimund Ubar, Digitaalsüsteemide juhtseadmete testide genereerimise meetodite uurimine ja väljatöötamine, 2002. (Investigation and Development of Test Generation Methods for Control Part of Digital Systems), Tallinn University of Technology School of Information Technologies.
Marina Brik, Research Master's Degree, 1994, (sup) Raimund Ubar, Mitmetastmeline testide generaator lõplike automaatide jaoks, 1994. (Test Synthesis for Finite State Machines), Tallinn University of Technology School of Information Technologies.
 
 
Additional information
Lectures and tutorials:

Feb 2010 TTÜ - Prof. Erik Larsson(Linköpingi University). Checking distributed properties to detect interconnect latency
post-doc Urban Ingelsson(Linköpingi University). Investigation into voltage and variation-aware manufacturing test

Veb 2010 TTÜ Linköping University Prof. Zebo Pengi lecture:
Challenges and Solutions for the Design of Fault-Tolerant Systems


Jan 2010- Windows 7 user's course
Certificate nr. 23949
IT training


Tutorials 2011:

June 2011 TUT - CREDES Summer School "Dependable Systems Design"
Feb 2011 TUT DCE - "High Level Synthesis of Digital Systems" prof. Samary Baranov (Bar Ilan University/School of Engineering, Ramat Gan, Israel)

Tutorials 2012:

Jan 2012 TUT- CREDES tutorial"HW System-Level Design and Modeling ESL Using C/C++, SystemC and TLM-2.0" prof. Zainalabedin Navabi (Worcester Polytechnic Institute, USA; University of Tehran, Iran)

Tutorials 2013:

RTL Design and Test with HDLs. Comprehensive FPGA and ASIC design course in two parts
February 11-14, 2013
Prof. Zainalabedin Navabi (Worcester Polytechnic Institute, USA; University of Tehran, Iran)

Tutorials 2014:

Seminar on IT standardisation
January 24, 2014
Taavi Valdlo

Various ENETA lectures and conferences (Microsoft Corporation)

ATI, CEBE seminars
incl.
Detsember 4, 2014 “Dealing with Physical Issues in Many-Cores” Prof. Zainalabedin Navabi, Worcester Polytechnic Institute, USA / University of Tehran, Iran

January 14, 2016 "Wireless Communication for Industrial Control: Test and Dependability for the Baseband-Processor" Prof. H.T. Vierhaus
November 10-11, 2015 "MEDIAN Finale" workshop in Tallinn

Publications

Category
Year
Publication
 
1.1.
2014
Jasnetski, Artjom; Ubar, Raimund; Tsertov, Anton; Brik, Marina (2014). Software-based self-test generation for microprocessors with high-level decision diagrams. Proceedings of the Estonian Academy of Sciences, 63 (1), 48−61.
3.1.
2014
Ubar, Raimund; Tsertov, Anton; Jasnetski, Artjokm; Brik, Marina. (2014). Software-based Self-Test Generation for Microprocessors with High-Level Decision Diagrams. Fortaleza, Brazil: IEEE Computer Society.
3.1.
2014
Kruus, Helena; Brik, Marina; Kruus, Margus; Ruberg, Priit; Viies, Vladimir; Ellervee, Peeter. (2014). Hardware Close Programming for Freshmen. Microelectronics Education (EWME), 10th European Workshop on : IEEE, 93−96.10.1109/EWME.2014.6877403.
3.1.
2012
Kruus, H.; Ubar, R.; Ellervee, P.; Gorev, M.; Pesonen, V.; Devadze, S.; Orasson, E.; Brik, M.; Min, M.; Annus, P.; Kruus, M.; Meigas, K. (2012). A Benchmark Suite for Evaluating the Efficiency of Test Tools. BEC 2012 : 13th biennial Baltic Electronics Conference : proceedings of the 13th biennial Baltic Electronics Conference : Tallinn University of Technology, October 3-5, 2012, Tallinn, Estonia. Tallinn, 2012: The 13th Biennial Baltic Electronics Conference (BEC2012). Tallinn University of Technology, 85−88.
3.2.
2012
Ubar, Raimund; Kostin, Sergei; Orasson, Elmet; Evartson, Teet; Brik, Marina (2012). A Tool for Teaching Hierarchical Fault Diagnosis in Digital Circuits. Proc. of 9th European Workshop on Microelectronics Education – EWME’12. Grenoble, France: CNRS, 1−4.
1.2.
2011
Kostin, Sergei; Ubar, Raimund; Raik, Jaan; Brik, Marina (2011). Hierarchical Physical Defect Reasoning in Digital Circuits. Estonian Journal of Engineering, 17 (3), 1−15.
3.1.
2009
Kostin, Sergei; Ubar, Raimund; Raik, Jaan; Aarna, Margit; Brik, Marina; Wuttke, Heinz-Dietrich (2009). Teaching Research in the Laboratory Using Diagnosis Environment for Digital Systems. 20th EAEEIE Conference Formal Proceedings: 20th EAEEIE Annual Conference on Innovation in Education for Electrical and Information Engineering, Valencia, Spain, June 22-24, 2009. IEEE, 1−4. DOI: 10.1109/EAEEIE.2009.5335462.
3.1.
2008
Ubar, Raimund; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Brik, Marina; Instenberg, Martin; Wuttke, Heinz-Dieter (2008). Diagnostic Modeling of Microprocessors with High-Level Decision Diagrams. In: 11th Biennial Baltic Electronics Conference (147−150). . IEEE.
3.1.
2006
Ubar, Raimund; Brik, Marina; Jutman, Artur; Raik, Jaan; Bengtsson, Tomas; Kumar, Shashi (2006). Functional Test Generation for Finite State Machines. Proceedings of the Baltic Electronics Conference: Baltic Electronics Conference, Laulasmaa, oktoober 2006. IEEE, 205−208.
3.4.
2006
Robal, T.;Brik, M.; Aarna, M. (2006). e-Learning of Digital Logic. Using e-Environments in Teaching Digital Logic. EWME 2006 Proceedings: 6th International Workshop on Microelectronics Education. Ed. L-R Zheng, J. Nurmi, J. Liu, R.Weerasekera, H. Tenhunen. Stockholm, Sweden: Royal Institue of Technology KTH, 120−123.
3.4.
2005
Brik, M.; Fomina, E.; Ubar, R. (2005). A Proposal for Optimization of Low-Powered FSM Testing. Proceedings of the East West Design Test Workshop (IEEE EWDTW’05) (15−20).. Odessa: EWDTW.
3.4.
2005
Fomina, E.; Vassilyev, R.; Brik, M. (2005). A New Approach to State Encoding of Low Power FSM. Proc. of the East West Design Test Workshop. Odessa: EWDTW, 21−26.
3.1.
2004
Brik, Marina; Raik, Jaan; Ubar, Raimund; Ivask, Eero (2004). On using genetic algorithm for test generation. 9th Biennial Baltic Electronics Conference. , 233−236.
3.2.
2004
Ubar, Raimund-Johannes; Aarna, Margit; Brik, Marina; Raik, Jaan (2004). High level fault modeling in digital systems. In: Shaker Verlag (486−491). . Aachen: Shaker Verlag.
3.4.
2004
Brik, M.; Raik, J.; Ubar, R.; Ivask, E. (2004). GA-based Test Generation for sequential circuits. Proc. of East-West Design&Test Workshop(EWDTW'04): Ukraine, September 23-26, 2004. , 30−34.
3.4.
2004
Ubar, R.; Aarna, M.; Brik, M.; Evartson, T.; Raik, J. (2004). High Level Fault Models for Digital Systems. University Research, Industry, International Cooperation: Minsk. Minsk, 303−310.
1.2.
2002
Ubar, R.; Raik, J.; Ivask, E.; Brik, M. (2002). Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta universitatis - series Electronics and Energetics, 15 (1), 123−136.
2.3.
2002
Brik, M. (2002). Investigation and Development of Test Generation Methods for Control Part of Digital Systems. (Doktoritöö, Tallinna Tehnikaülikool). Tallinn: Tallinn Technical University Press.
3.1.
2002
Ubar, R.; Raik, J.; Ivask, E.; Brik, M. (2002). Mixed-level defect simulation in data-paths of digital systems, Microelectronics. MIEL 2002. 23rd International Conference, 2: 12-15 May 2002. IEEE Computer Society Press, 617−620.
3.1.
2002
Ubar, Raimund; Raik, Jaan; Ivask, Eero; Brik, Marina (2002). Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. Proceedings of the IEEE Workshop on Electronic Design, Test and Applications – DELTA’02: Christchurch, New Zealand, 29-31 January 2002. IEEE Computer Society Press, 86−91.
3.4.
2002
Ubar, R.; Raik, J.; Ivask, E.; Brik, M. (2002). Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the International Conference on Computer Dependability: Tomsk, Russia, September 10-13, 2002. , 315−319.
3.4.
2001
Ubar, R.; Raik, J.; Ivask, E.; Brik, M. (2001). Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 2: 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2001. , 617−620.
3.4.
2000
Brik, Marina; Raik, Jaan; Ubar, Raimund (2000). Hierarchical fault simulation for finite state machines. 7th Baltic Electronics Conference, Tallinn, October 8-11. , 145−148.
3.4.
2000
Ubar, R.; Brik, M. (2000). Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems: Gdynia (Poland), June 15-17, 2000. 533−538.
3.4.
1999
Brik, M.; Ubar, R. (1999). Two-Level Simulation-Based Test Generation for Finite State Machines. IEEE 17th NORCHIP Conference, Oslo, Nov. 8-9, 1999. 211−216.
3.1.
1998
Brik, Marina; Jervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund (1998). Hierarchical Test Generation for Digital Systems. Mixed Design of Integrated Circuits and Systems (131−136). . Kluwer Academic Publishers.
3.4.
1998
Brik, M.; Ubar, R. (1998). An improved test generation approach for sequential circuits using decision diagrams. 6th Biennial Conference on Electronics and Microsystems Technology: Tallinn, 1998. 155−158.
1.2.
1997
Brik, Marina; Jervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund (1997). Mixed-Level Test Generator for Digital Systems. Proceedings of the Estonian Academy of Sciences. Engineering, 3 (4), 271−282.
3.4.
1997
Brik, M.; Jervan, G.; Markus, A.; Raik, J.; Ubar, R. (1997). A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. 4-th International Workshop on Computer Aided Design of Modern Devices and ICs., Poznan, Poland, June 12-14, 1997. , 415−420.
3.1.
1996
Ubar, R.; Brik, M. (1996). Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. Lecture Notes in Computer Science No 1150. Dependable Computing - EDCC-2 (268−281).. Springer Verlag.
3.4.
1996
Ubar, R.; Brik, M. (1996). Test generation for finite state machines. BEC '96. The 5th Biennial Baltic Electronics Conference. Proceedings (233−236).. Tallinn: Tallinn Technical University.
3.4.
1994
"Dušshina, Julia;Brik, Marina" (1994). Test generation for control faults in digital systems. 1: BEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia).. Tallinn: Tallinna Tehnikaülikool, 325−330.
3.4.
1994
"Brik, Marina;Ubar, Raimund-Johannes" (1994). Hierarchical test generation for finite state machines. 1: BEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia).. Tallinn, 319−324.
7.01.2019

Otsi projekti

  • {{item.Name}}
Asutus on projekti finantseerija   Asutus on projekti teostaja  
  • {{searchListItem.Name}}
Kõik   Tavaprojektid   Ülemprojektid   Alamprojektid  
Uus Frascati (2015)
Uus ja vana Frascati (otsing uue järgi väljastab ka seotud vanad)
Kõik
Käimasolevad
Lõppenud
Algus
Hajus
Täpne
Lihtotsing Tühjenda
  • Leitud 13 kirjet
ProgrammLiikNumberNimiProjekti algusProjekti lõppVastutav täitjaAsutusFinantseerijapoolne rahastamine
ETFETF5649Digitaalskeemide defekt-orienteeritud diagnostika01.01.200331.12.2006Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond40 819,99 EUR
SFSF0142508s03Digitaalsüsteemide disain ja test01.01.200331.12.2007Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond658 321,94 EUR
MUUT244 (0140244s98)Digitaalsüsteemide projekteerimise ja diagnostika alased uuringud, väljatöötlused ja rakendused01.01.199831.12.2002Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 417 982,18 EUR
MUUG4300 (ETF4300)Disainivigade diagnostika digitaalskeemides ja -süsteemides01.01.200031.12.2003Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 37 447,75 EUR
MUUBF39EÜ 6. raamprogrammi teadusprojekti (STREP) kaasfinantseerimine06.04.200631.12.2006Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 13 741,00 EUR
TKTAR8077Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus CEBE07.07.200831.08.2015Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut2 066 263,60 EUR
ETFETF7483Isediagnoosivad digitaalsüsteemid01.01.200831.12.2011Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond55 414,27 EUR
ETFETF5910Isetestivad digitaalsüsteemid01.01.200431.12.2007Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond51 822,58 EUR
MUUV334IST STREP projekt VERTIGO - sardsüsteemide projekteerimise platvormi verifitseerimine ja valideerimine01.06.200631.12.2008Jaan RaikTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut208 837,70 EUR
SFSF0140041s08Töökindlate sardsüsteemide disain01.01.200831.12.2013Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond1 504 530,37 EUR
IUTIUT19-1Usaldusväärsed mitmetuumalised arvutisüsteemid01.01.201431.12.2019Jaan RaikTallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut1 572 000,00 EUR
MUUV170Uurimis- ja õppetöö meetodid valdkonnas 'Ühekiibisüsteemide disain'01.12.200130.11.2004Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 124 627,71 EUR
MUUV195Virtuaalse infotehnoloogia teadusliku uurimis- ja arendustöö tippkeskuse rajamine01.11.200231.08.2005Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 137 346,13 EUR