See veebileht kasutab küpsiseid kasutaja sessiooni andmete hoidmiseks. Veebilehe kasutamisega nõustute ETISe kasutustingimustega. Loe rohkem
Olen nõus

Sergei Devadze

https://www.etis.ee/CV/Sergei_Devadze/est
5.01.1981
6202246
sergei.devadze@ttu.ee
O-3721-2019
Google Scholar ID:
https://scholar.google.com/citations?user=5z2HBJ4AAAAJ

Teenistuskäik

Töökohad ja ametid
01.01.2017–...   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut, Teadur (1,00)
01.09.2010–31.12.2016   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Teadur (0,50)
01.01.2010–30.06.2015   
ELIKO Tehnoloogia Arenduskeskus OÜ, Eesti Tehnoloogia Arenduskeskus (ELIKO OÜ), arendusinsener (0,50)
01.09.2007–30.06.2008   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Info- ja kommunikatsioonitehnoloogia doktorikool, Teadur (0,25)
01.01.2007–31.08.2010   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide projekteerimise õppetool , Teadur (1,00)
2005–2006   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, insener (1,00)
01.01.2004–31.12.2005   
Eesti Tehnoloogia Arenduskeskus (ELIKO OÜ), arendusinsener
2001–2005   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, insener (0,25)
 
 
Haridustee
2004–2009   
Tallinna Tehnikaülikool, doktoriõpe, info- ja kommunikatsioonitehnoloogia
2003–2004   
Tallinna Tehnikaülikool, magistriõpe, arvuti- ja süsteemitehnika eriala
1999–2003   
Tallinna Tehnikaülikool, bakalaureuseõpe, arvuti- ja süsteemitehnika eriala

Kvalifikatsioon

Teaduskraadid
Sergei Devadze, doktorikraad, 2009, (juh) Raimund Ubar; Peeter Ellervee, Fault Simulation of Digital Systems (Digitaalsüsteemide rikete simuleerimine), Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool.
 
 
Teaduspreemiad ja tunnustused
2007, Sergei Devadze, Eesti Infotehnoloogia Sihtasutus (EITSA) Stipendium
2006, Sergei Devadze, Eesti Infotehnoloogia Sihtasutus (EITSA) Stipendium
2005, Sergei Devadze, Eesti Infotehnoloogia Sihtasutus (EITSA) Stipendium
2004, Sergei Devadze, Eesti Infotehnoloogia Sihtasutus (EITSA) Stipendium
2003, Sergei Devadze, Üliõpilaste teadustööde riikliku konkursi I preemia
 
 
Teadustöö põhisuunad
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.8. Elektrotehnika ja elektroonika
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.8. Elektrotehnika ja elektroonika; CERCS KLASSIFIKAATOR: T171 Mikroelektroonika ; TÄPSUSTUS: Keerukate trükplaatide testimise meetodid, mikroprotsessor-põhine ja FPGA-põhine trükplaatide test
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.7. Info- ja kommunikatsioonitehnoloogia; TÄPSUSTUS: Digitaalsüsteemide diagnostika, Digitaalskeemide rikete simuleerimine, Keerukate digitaalsüsteemide sünteesi meetodid ja algoritmid
 
 
Lisainfo
ETF9423 projekti vastutav täitja ("Kiibisisesed instrumendid elektroonikasüsteemide testimiseks", 01.01.2012−31.12.2015)

Lõppenud projektid

Juhendamisel väitekirjad

Juhendatud väitekirjad

Publikatsioonid

1.1. Teadusartiklid, mis on kajastatud Web of Science andmebaasides Science Citation Index Expanded, Social Sciences Citation Index, Arts & Humanities Citation Index, Emerging Sources Citation Index ja/või andmebaasis Scopus (v.a. kogumikud)
 
Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; ter Braak, Timon D.; Devadze, Sergei; Fey, Goerschwin; Jenihhin, Maksim; Jutman, Artur; Kerkhoff, Hans G.; Könighofer, Robert; Koyfman, Shlomit; Malburg, Jan; Moran, Shiri; Raik, Jaan; Rauwerda, Gerard; Riener, Heinz; Röck, Franz; Shibin, Konstantin; Sunesen, Kim; Wan, Jinbo ... Zhao, Yong (2018). Designing Reliable Cyber-Physical Systems. Lecture Notes in Electrical Engineering, 454, 15−38.10.1007/978-3-319-62920-9_2.
 
Kõusaar, Jaak; Ubar, Raimund; Kostin, Sergei; Devadze, Sergei; Raik Jaan (2018). Exact Parallel Critical Path Fault Tracing to Speed-Up Fault Simulation in Sequential Circuits. International Journal of Microelectronics and Computer Science, 9 (1), 9−18.
 
Shibin, Konstantin; Jutman, Artur; Devadze, Sergei; Grabmann, Martin; Pricken, Robin (2017). Health Management for Self-Aware SoCs based on IEEE 1687 Infrastructure. IEEE Design and Test, 1−6.10.1109/MDAT.2017.2750902.
 
Aleksejev, I.; Jutman, A.; Devadze, S. (2017). Run-Time Reconfigurable Instruments for Advanced Board-Level Testing. IEEE Instrumentation & Measurement Magazine, 20 (4), 23−30.10.1109/MIM.2017.8006390.
 
Aleksejev Igor; Jutman Artur; Devadze Sergei; Shibin Konstantin (2016). Optimization of Boundary Scan Tests using FPGA-based Efficient Scan Architectures. Journal of Electronic Testing-Theory and Applications, 245−255.
 
Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J. (2015). Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocessors and Microsystems, 1−10.10.1016/j.micpro.2015.05.003.
 
Gorev, M.; Ubar, R.; Ellervee, P.; Devadze, S.; Raik, J.; Min, M. (2015). Functional Self-Test of High-Performance Pipe-Lined Signal Processing Architectures. Microprocessors and Microsystems, 39 (8), 909−918.10.1016/j.micpro.2014.11.002.
 
Ubar, Raimund; Kostin, Sergei; Kruus, Helena; Aarna, Margit; Devadze, Sergei (2014). Environment for Analysis of Functional Self-Test Quality in Digital Systems. Proceedings of the Estonian Academy of Sciences, 2 (63), 151−162.
 
Jutman, Artur; Devadze, Sergei; Shibin, Konstantin (2013). Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. IEEE Design & Test of Computers, 30 (5), 26−35.10.1109/MDAT.2013.2278535.
 
Raik, J.; Ubar, R.; Devadze, S.; Jutman, A (2005). Efficient single-pattern fault simulation on structurally synthesized bdds. Lecture Notes in Computer Science, 3463, 332−344.
1.2. Teadusartiklid teistes rahvusvahelistes teadusajakirjades, millel on registreeritud kood, rahvusvaheline toimetus, rahvusvahelise kolleegiumiga eelretsenseerimine, rahvusvaheline levik ning kättesaadavus ja avatus kaastöödele
 
Tsertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, Artjom (2014). In-System Programming of Non-Volatile Memories on Microprocessor-centric Boards. International Journal of Microelectronics and Computer Science, 5 (1), 25−34.
 
Tsertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, Artjom (2013). On In-System Programming of Non-volatile Memories (Extended). International Journal of Microelectronics and Computer Science, 4 (2), 72−78.
 
Shibin, Konstantin; Devadze, Sergei; Rosin, Vjatseslav; Jutman, Artur; Ubar, Raimund (2012). Open-Source JTAG Simulator Bundle for Labs. International Journal of Electronics and Telecommunications, 58 (3), 233−239. DOI: 10.2478/v10177-012-0032-4.
 
Ivask, Eero; Devadze, Sergei; Ubar, Raimund. (2011). Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Computing: Practice and Experience, Vol 12, 153-163.
 
Ivask, E.; Devadze, S.; Ubar, R. (2010). Distributed Approach for Parallel Exact Critical Path Tracing Fault Simulation. International Journal of Microelectronics and Computer Science, 1 (2), 165−174.
 
Ubar, R.; Jutman, A.; Kruus, M.; Orasson, E.; Devadze, S.; Wuttke, H.-D. (2007). Learning Digital Test and Diagnostics via Internet. International Journal of Online Engineering, 3 (1), 1−9.
2.3. Dissertatsioonide seerias ilmunud dissertatsioonid (v.a. käsikirjalised);
 
Devadze, Sergei (2009). Fault simulation of digital systems. (Doktoritöö, Tallinna Tehnikaülikool). Tallinn: Tallinn University of Technology Press.
3.1. Artiklid/peatükid lisas loetletud kirjastuste välja antud kogumikes (kaasa arvatud Web of Science Book Citation Index, Web of Science Conference Proceedings Citation Index, Scopus refereeritud kogumikud)
 
Ehrenberg H.; Odintsov S.; Devadze S.; Jutman A.; Aleksejev I.; Wenzel T.; (2019). Ways for board and system test to benefit from FPGA embedded synthetic instrumentation. Proc. of AUTOTESTCON’2019, Maryland, USA, 2019: AUTOTESTCON’2019, National Harbor, Maryland, USA, Aug 26-29, 2019. IEEE, 1−10. DOI: 10.1109/AUTOTESTCON43700.2019.8961057.
 
Jürimägi, Lembit; Ubar, Raimund; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Oyeniran, Adeboye. (2019). Application Specific True Critical Paths Identification in Sequential Circuits. 2019 25th IEEE International Symposium on On-Line Testing and Robust System Design: 25th IEEE International Symposium on On-Line Testing and Robust System Design Hotel Rodos Palace, Rhodes Island, Greece July 1-3, 2019. IEEE Computer Society, 1−6 [ilmumas].
 
Jürimagi, Lembit; Ubar, Raimund; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei (2018). Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Platja D'Aro, Hispaania, 2018. IEEE, 1−6.
 
Kõusaar, Jaak; Ubar, Raimund; Kostin, Sergei; Devadze, Sergei; Raik, Jaan (2018). Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. 25th International Conference Mixed Design of Integrated Circuits and Systems – MIXDES. Gdynia, Poland, June 21-23, 2018.. ieee, 305−310.
 
Tsertov, Anton; Jutman, Artur; Shibin, Konstantin; Devadze, Sergei (2018). IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring. 2018 IEEE AUTOTESTCON: AUTOTESTCON’2018, National Harbor, Maryland, USA, Sept 17-20, 2018. Piscataway, NJ, USA: IEEE, 1−9.10.1109/AUTEST.2018.8532559.
 
Odintsov, Sergei; Jutman, Artur; Devadze, Sergei; Aleksejev, Igor (2017). Embedded Instrumentation Toolbox for Screening Marginal Defects and Outliers for Production. Proc. of AUTOTESTCON’2017, Schaumburg, USA, Sept 11-14, 2017: AUTOTESTCON2017, Schaumburg, Illinois, USA, September 11-14, 2017. IEEE,.
 
Odintsov, Sergei; Jutman, Artur; Devadze, Sergei (2017). Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus. Proc of 48th IEEE International Test Conference (ITC’2017): IEEE International Test Conference (ITC’2017). Fort Worth, TX, USA, Oct 31 - Nov 2: IEEE,.
 
Shibin, Konstantin; Devadze, Sergei; Jutman, Artur (2016). On-line Fault Classification and Handling in IEEE1687 based Fault Management System for Complex SoCs. IEEE, 69−74.
 
Aleksejev, I.; Devadze, S.; Jutman, A. (2016). On Coverage of Timing Related Faults at Board Level. IEEE 21st European Test Symposium, Amsterdam, Netherlands, May 24 – May 27. IEEE, 1−2.10.1109/ETS.2016.7519295.
 
Aleksejev Igor; Jutman Artur; Devadze Sergei (2016). Run-Time Reconfigurable Instruments for Advanced Board-Level Testing. AUTOTESTCON 2016. USA: IEEE, 1−8.
 
Tšertov, Anton; Jutman, Artur; Devadze, Sergei; Sonza-Reorda, Matteo; Larsson, Erik; Ghani Zadegan, Farrokh; Cantoro, Riccardo; Montazeri, Mehrdad; Krenz-Baath, Rene (2016). A Suite of IEEE 1687 Benchmark Networks. Proc of 47th IEEE International Test Conference (ITC’2016): IEEE International Test Conference (ITC’2016), Fort Worth, TX, USA, Nov 15-17, 2016. IEEE, paper 6.1.
 
Jutman, Artur; Shibin, Konstantin; Devadze, Sergei (2016). Reliable Health Monitoring and Fault Management Infrastructure based on Embedded Instrumentation and IEEE 1687. Proc. of AUTOTESTCON’2016, Anaheim, USA, Sept 12-15, 2016: AUTOTESTCON’2016, Anaheim, USA, Sept 12-15, 2016. IEEE, 240−249.
 
Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; ter Braak, Timon; Devadze, Sergei; Fey, Goerschwin; Jenihhin, Maksim; Jutman, Artur; Kerkhoff, Hans G.; Koenighofer, Robert; Malburg, Jan; Moran, Shiri; Raik, Jaan; Rauwerda, Gerard; Riener, Heinz; Roeck, Franz; Shibin, Konstantin; Sunesen, Kim; Wan, Jinbo; Zhao, Yong (2016). Designing Reliable Cyber-Physical Systems Overview associated to the Special Session at FDL'16. NEW YORK: IEEE.
 
Ubar, Raimund; Kõusaar, Jaak; Gorev, Maksim; Devadze, Sergei (2015). Combinational Fault Simulation in Sequential Circuits. In: Proceedings of International Symposium on Circuits and Systems (2876−2879). Lisbon, Portugal, 24-27 May, 2015: IEEE Computer Society Press.10.1109/ISCAS.2015.7169287.
 
Gorev, Maksim; Ubar, Raimund; Devadze, Sergei (2015). Fault Simulation with Parallel Exact Critical Path Tracing in Multiple Core Environment. In: Proceedings of IEEE Conference on Design, Automation & Test in Europe – DATE-2015 (1−6).. Grenoble, France, 9-13 March, 2015: IEEE Computer Society Press.
 
Aleksejev, Igor; Jutman, Artur; Devadze, Sergei; Shibin, Konstantin (2015). Virtual Reconfigurable Scan-chains on FPGAs for Optimized Board Test. 16th IEEE Latin-American Test Symposium (LATS), Puerto Vallarta, Mexico, March 25 - 27, 2015. Puerto Vallarta, Mexico: IEEE, 1−6.10.1109/LATW.2015.7102411.
 
Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J. (2014). Critical Path Tracing based Simulation of Transition Delay Faults. 17th Euromicro Conference on Digital System Design, Verona, Italy, August 27-29, 2014. IEEE Computer Society.
 
Shibin, Konstantin; Jutman, Artur; Devadze, Sergei (2014). Asynchronous fault detection in IEEE P1687 instrument network. North Atlantic Test Workshop 2014. IEEE, 73−78.10.1109/NATW.2014.24.
 
Ghani Zadegan, Farrokh; Larsson, Erik; Jutman, Artur; Devadze, Sergei; Krenz-Baath, Rene (2014). Design, Verification and Application of IEEE 1687. Proceedings of 23rd Asian Test Symposium (ATS): Asian Test Symposium (ATS), Hangzhou, China, 2014. Hangzhou, China: IEEE, 93−100.10.1109/ATS.2014.28.
 
Gorev, M.; Ubar, R.; Ellervee, P.; Devadze, S.; Raik, J.; Min, M. (2013). At-Speed Self-Testing of High-Performance Pipe-Lined Processing Architectures. 2013 NORCHIP: 11–12 November, 2013 Vilnius, LITHUANIA: The 31st Norchip Conference, Vilnius, Lithuania, Nov. 2013. IEEE, 1−6.10.1109/NORCHIP.2013.6702000.
 
Tsertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, Artjom (2013). On In-System Programming of Non-volatile Memories. Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2013, Gdynia, Poland, June 20-22, 2013. IEEE, 408−413.
 
Kruus, H.; Ubar, R.; Ellervee, P.; Gorev, M.; Pesonen, V.; Devadze, S.; Orasson, E.; Brik, M.; Min, M.; Annus, P.; Kruus, M.; Meigas, K. (2012). A Benchmark Suite for Evaluating the Efficiency of Test Tools. BEC 2012 : 13th biennial Baltic Electronics Conference : proceedings of the 13th biennial Baltic Electronics Conference : Tallinn University of Technology, October 3-5, 2012, Tallinn, Estonia. Tallinn, 2012: The 13th Biennial Baltic Electronics Conference (BEC2012). Tallinn University of Technology, 85−88.
 
Jutman, Artur; Devadze, Sergei; Aleksejev, Igor; Wenzel, Thomas (2012). Embedded Synthetic Instruments for Board-Level Testing. IEEE 17th European Test Symposium, Annecy, France, May 28 – June 1. IEEE Computer Society,.
 
Aleksejev, Igor; Jutman, Artur; Devadze, Sergei; Odintsov, Sergei; Wenzel, Thomas (2012). FPGA-Based Synthetic Instrumentation for Board Test. 43th IEEE International Test Conference, Anaheim, CA, USA, Nov 4-9, 2012. IEEE Computer Society, 1−6.
 
Tsertov, Anton; Jutman, Artur; Devadze, Sergei; Ubar, Raimund (2011). Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Proceedings of 20th Asian Test Symposium (ATS): Asian Test Symposium (ATS), New Delhi, India, 2011. New Delhi, India, 532−538.10.1109/ATS.2011.79.
 
Jutman, Artur; Devadze, Sergei; Aleksejev, Jevgeni (2011). Invited paper: System-Wide Fault Management based on IEEE P1687 IJTAG. 6th IEEE Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, June 20-22, 2011 (1−6).. IEEE Computer Society.
 
Tsertov, Anton; Jurman, Artur; Ubar, Raimund; Devadze, Sergei (2011). Board-Level Modeling for PCB Testing. Proceedings of 14th Euromicro Conference on Digital System Design (1−6).. Oulu, Finland: IEEE Computer Society.
 
Ubar, Raimund; Mironov, Dmitri; Devadze, Sergei; Raik, Jaan; Jutman, Artur (2011). Digital Logic Simulation with Compressed BDDs. Proceedings of 2011 IEEE International Conference on Computer Science and Automation Engineering (CSAE), 3: 2011 IEEE International Conference on Computer Science and Automation Engineering, Shanghai, China, 10 - 12 Jun, 2011. IEEE Computer Society, 105−109.
 
Ubar, Raimund; Devadze, Sergei (2011). Fast Parallel Fault Reasoning in Digital Circuits. Design and Test Technology for Dependable Systems-on-chip (310−335).. USA, Hershey - New York: IGI Publishing.
 
Ivask, Eero; Devadze, Sergei; Ubar, Raimund (2010). Collaborative Distributed Fault Simulation for Digital Electronic Circuits. Intelligent Distributed Computing IV: 4th International Symposium on Intelligent Distributed Computing - IDC 2010, Tangier, Marocco, September 2010. Ed. Mohammad Essaaidi, Michele Malgeri, Costin Badica. Springer, 67−76. (Studies in Computational Intelligence).
 
Tsertov, Anton; Jutman, Artur; Devadze, Sergei. (2010). Testing Beyond the SoCs in a Lego Style. Proceedings of IEEE East-West Design & Test Symposium (EWDTS’10): IEEE East-West Design & Test Symposium (EWDTS’10). IEEE, 334−338.10.1109/EWDTS.2010.5742052.
 
Mironov, D.; Ubar, R.; Devadze, S.; Raik, J.; Jutman, A. (2010). Structurally Synthesized Multiple Input BDDs for Speeding up Logic-Level Simulation of Digital Circuits. Proc. of the 13th Euromicro Conference on Digital System Design – DSD’2010: 13th Euromicro Conference on Digital System Design – DSD’2010. Lille, France, Sept.1-3, 2010. IEEE, 658−663.10.1109/DSD.2010.27.
 
Ivask, Eero; Devadze, Sergei; Ubar, Raimund (2010). Distributed Approach for Parallel Exact Critical Path Tracing Fault Simulation. Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2010 : Wroclaw, Poland 24 - 26 June, 2010. Ed. Andrzej Napieralski. IEEE, 471−476.
 
Ivask, E.; Devadze, S.; Ubar, R. (2010). Collaborative Distributed Computing in the Field of Digital Electronics Testing. Information Technology for Balanced Automation Systems: BASYS 2010, Valencia, Spain, July 21-23. Springer, 145−152.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur. (2010). Parallel X-Fault Simulation with Critical Path Tracing Technique. In: Kathy Preas (Ed.). Proceedings of Design, Automation & Test in Europe : Dresden, Germany March 8-12, 2010 (879−884). . IEEE Computer Society Press.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur. (2010). Fast Fault Simulation for Extended Class of Faults in Scan-Path Circuits. Proc. of 5th IEEE Int. Symposium on Electronic Design, Test and Applications - DELTA 2010 (14−19). . Los Alamitos, California, USA: IEEE Computer Society.
 
Devadze, S.; Jutman, A.; Tsertov, A.; Ubar, R. (2009). Microprocessor Modeling for Board Level Test Access Automation. Proc. of 10th IEEE Workshop on RTL and High Level Testing: 10th IEEE Workshop on RTL and High Level Testing, Hong Kong, Nov. 27-28, 2009. IEEE, 154−159.
 
Devadze, S.; Jutman, A.; Aleksejev, I.; Ubar, R. (2009). Fast Extended Test Access via JTAG and FPGAs. Proc. of 40th International Test Conference - ITC’2009: 40th International Test Conference - ITC’2009, Austin, Texas, Nov. 1-6, 2009. paper 2.3−pp- 1-7.
 
Devadze, Sergei; Jutman, Artur; Aleksejev, Igor; Ubar, Raimund (2009). Turning JTAG inside out for fast extended test access. 10th IEEE Latin American Test Workshop, 2-5 March, 2009, Buzios, Brazil. Buzios, Brazil: IEEE, 1−6.
 
Devadze, Sergei; Ubar, Raimund; Raik, Jaan; Jutman, Artur (2009). Parallel Exact Critical Path Tracing Fault Simulation with Reduced Memory Requirements. In: 4th IEEE Int. Conf. on Design and Technology of Integrated Systems in Nanoscale Era – DTIS’09, Cairo, Egypt, April 6-7, 2009 (155−160). . IEEE Computer Society Press.
 
Ferreira, J.M.; Sousa, E.; Ubar, R.; Jutman, A.; Devadze, S. (2009). Remote boundary-scan testing through micro-webservers. Proc. of 3rd IEEE International Conference on e-Learning in Industrial Electronics - ICELIE'2009: 3rd IEEE International Conference on e-Learning in Industrial Electronics - ICELIE'2009. Portugal, Porto,.
 
Devadze, Sergei; Jutman, Artur; Tsertov, Anton; Instenberg, Martin; Ubar, Raimund (2008). Microprocessor-based System Test using Debug Interface. In: 26th IEEE NORCHIP Conference (40.10).. IEEE.
 
Devadze, Sergei (2008). Software Environment for Synthesis of Testable FSM through Decomposition. IEEE 26th International Conference on Microelectronics (MIEL 2008), Nis, Serbia. 433−436.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur (2008). Parallel Fault Backtracing for Calculation of Fault Coverage. The 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008). IEEE Computer Society Press, 667−672.
 
Ubar, Raimund; Devadze, Sergei; Jenihhin, Maksim; Raik, Jaan; Jervan, Gert; Ellervee, Peeter (2008). Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. IEEE International Symposium on Electronic Design, Test and Applications (DELTA), January 23 - 25, 2008, Hongkong. IEEE Computer Society Press, 222−227.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur (2007). Ultra Fast Parallel Fault Analysis on Structural BDDs. In: Proceedings 12th IEEE European Test Symposium – ETS 2007 (131−136). . IEEE Computer Society Press.
 
Sudnitson, Alexander; Devadze, Sergei (2007). Web-Based Computer Aided Design Support of Finite State Machine Additive Decomposition for Low Power. 5th IEEE East-West Design & Test International Symposium. 494−498.
 
Devadze, Sergei; Raik, Jaan; Jutman, Artur; Ubar, Raimund. (2006). Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using Structurally Synthesized BDDs. Proceedings of 7th IEEE Latin-American Test Workshop (97−102). . IEEE Computer Society Press.
 
"Devadze, Sergei;Sudnitsõn, Aleksander" (2005). FSM decomposition software for education and research. Proc. IEEE EUROCON 2005 International Conference on Computer as a tool : Belgrade, Serbia & Montenegro. Belgrad: TTY puuduv kirjastus, 839−842.
 
Devadze, Sergei; Fomina, Jelena; Kruus, Margus; Sudnitsõn, Aleksander (2003). Web-based system for sequential machines decomposition. In: EUROCON 2003. Computer as a Tool. (57−61).. [S. l.]: IEEE.
 
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2002). Java Technology Based Training System for Teaching Digital Design and Test. Proc. of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002: 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002. 283−286.
3.2. Artiklid/peatükid lisas mitte loetletud kirjastuste välja antud kogumikes
 
Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; ter Braak, Timon; Devadze, Sergei; Fey, Goerschwin; Jenihhin, Maksim; Jutman, Artur; Kerkhoff, Hans G.; Könighofer, Robert; Malburg, Jan; Moran, Shiri; Raik, Jaan; Rauwerda, Gerard; Riener, Heinz; Röck, Franz; Shibin, Konstantin; Sunesen, Kim; Wan, Jinbo; Zhao, Yong (2016). Designing Reliable Cyber-Physical Systems. In: ECSI FDL 2016 Forum on specification & Design Languages, September 14-16, 2016 Bremen, Germany (1−8). ECSI.
 
Bedoya, C. F.; Cela, J. M.; Fouz, M. C.; Francia, D.; Navarro, A.; Puerta, J.; Sastre, J.; Redondo, I.; Beni, N; Szillasi, Z.; Balbi, G.; Baldanza, C.; Cafaro, V.; Cavallo, F.R.; Codispoti, G.; Dallavalle, G.M.; Giordano, V.; Guiducci, L; Masetti, G.; Siroli, G.P. ... Devadze, S. (2015). CMS Drift Tubes Sector Collector Relocation Phase 1 Upgrade. In: The CMS Experiment Detector Note (1−41).. Geneva, Switzerland: CERN.
 
Ubar, Raimund; Jutman, Artur; Raik, Jaan; Devadze, Sergei; Aleksejev, Igor; Chepurov, Anton; Chertov, Anton; Kostin, Sergei; Orasson, Elmet; Wuttke, H.-D. (2010). E-Learning Environment for WEB-Based Study of Testing. Proc. of the 8th European Workshop on Microelectronics Education - EWME 2010: 8th European Workshop on Microelectronics Education - EWME 2010. Saksamaa, Darmstadt, 47−52.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur (2007). Parallel Fault Backtracing for Calculation of Fault Coverage. In: International Conference on Microelectronics, Devices and Materials and the Workshop on Electronic Testing (MIDEM'07) Proceedings (165−170). . Slovenia: MIDEM Society for Microelectronics, Electronic Components and Materials.
 
Ubar, Raimund; Jutman, Artur; Devadze, Sergei; Wuttke, Hans-Dietrich (2007). Bringing Research Issues into Lab Scenarios on the Example of SOC Testing. In: ICEE Proceedings (N/A).. University of Coimbra.
 
Devadze, Sergei; Kruus, Margus; Sudnitsõn, Aleksander (2001). Web-based software implementation of finite state machine decomposition for design and education. Proc. International Conference on Computer Systems and Technologies : CompSys'2001 : Sofia, Bulgaria, 2001.
3.4. Artiklid/ettekanded, mis on avaldatud valdkonda 3.1. mittekuuluvates konverentsikogumikes
 
Jutman, Artur; Devadze, Sergei; Shibin, Konstantin (2016). Synchronization, Calibration and Triggering of IEEE 1687 Embedded Instruments. Proc. of the 17th Workshop on RTL and High Level Testing (WRTLT’2016): 17th Workshop on RTL and High Level Testing (WRTLT’2016), Nov. 24-25, 2016, Hiroshima, Japan. IEEE, 1−6.
 
Shibin, Konstantin; Jutman, Artur; Devadze, Sergei (2013). Fault Management Instrumentation Network based on IEEE P1687 IJTAG. 18th IEEE European Test Symposium (PhD student work-in-progress Papers), May 27-31, 2013. IEEE Computer Society,.
 
Shibin, Konstantin; Aleksejev, Igor; Jutman, Artur; Devadze, Sergei (2012). IEEE P1687 IJTAG demonstrator on FPGA. DATE 2012 University Booth: Design Automation and Test in Europe, Dresden, Germany, March 12-16. Association for Computing Machinery (ACM),.
 
Pleskacz, Witold; Jutman, Artur; Ubar, Raimund; Devadze, Sergei (2007). DefSim – the defective IC. DATE 2007 University Booth: Design Automation and Test in Europe, Nice, France, April 16-20, 2007. Ed. Rudy Lauwereins, Jan Madsen. ACM, s96.
 
Sudnitson, Alexander; Sergei, Devadze (2006). Computer Aided Design Support of FSM Multiplicative Decomposition. IEEE East-West Design&Test International Workshop (EWDTW'06), Sochi, Russia. 241−246.
 
Devadze, S.; Gorjachev, R.; Jutman, A.; Orasson, E.; Rosin, V.; Ubar, R. (2003). E-Learning Tools for Digital Test. Distance Learning – Educational Environment of the XXI Century: Minsk, Nov. 13-15, 2003. 336−342.
 
Devadze, S.; Jutman, A.; Kruus, M.; Sudnitson, A.; Ubar, R. (2002). Web Based Tools for Synthesis and Testing of Digital Devices. Proc. International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002: International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002. I.91−I.96.
 
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R. (2002). Web-based training system for teaching basics of RT-level Digital Design, Test, and Design for Test. Proc. of 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002: 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002. 699−704.
 
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2002). Teaching Digital RT-Level Self-Test using a Java Applet. 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002. 322−328.
3.5. Artiklid/ettekanded, mis on avaldatud kohalikes konverentsikogumikes
 
Shibin, Konstantin; Jutman, Artur; Devadze, Sergei (2012). System-Wide Fault Management based on IEEE P1687 IJTAG. The Fourth Annual Conference of the National Doctoral School in Information and Communication Technologies, October 3 – 5, 2012, Laulasmaa SPA hotel.
 
Devadze, Sergei; Ubar, Raimund (2007). Parallel Fault Analysis on Structurally Synthesized BDDs. Teine IKTDK aastakonverents, Viinistu, 2007. Estonia, 47−50.
 
Devadze, Sergei (2006). Efficient Fault Simulation Method on Structurally Synthesized BDDs. Esimene IKTDK aastakonverents. Estonia, 123−126.
 
Devadze, Sergei (2003). Web-Based Training System for Teaching Digital Design and Test. Proc. of 7th International Student Conference on Electrical Engineering, (POSTER2003): 7th International Student Conference on Electrical Engineering, (POSTER2003). Prague, Czech Republic, IC6.

Tööstusomand

6.04.2020

Sergei Devadze

https://www.etis.ee/CV/Sergei_Devadze/eng
5.01.1981
6202246
sergei.devadze@ttu.ee
Google Scholar ID:
https://scholar.google.com/citations?user=5z2HBJ4AAAAJ

Career

Institutions and positions
01.01.2017–...   
Tallinn University of Technology , School of Information Technologies, Department of Computer Systems, Researcher (1,00)
01.09.2010–31.12.2016   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Researcher (0,50)
01.01.2010–30.06.2015   
ELIKO Competence Centre in Electronics-, Info- and Communication Technologies, Estonian Competence Centre (ELIKO OÜ), R&D engineer (0,50)
01.09.2007–30.06.2008   
Tallinn University of Technology , School of Information Technologies, Info- ja kommunikatsioonitehnoloogia doktorikool, Researcher (0,25)
01.01.2007–31.08.2010   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Design, Researcher (1,00)
2005–2006   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , engineer (1,00)
01.01.2004–31.12.2005   
Estonian Competence Centre (ELIKO OÜ), development engineer
2001–2005   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , engineer (0,25)
 
 
Education
2004–2009   
Tallinn University of Technology, Ph.D. study, Information and Communication Technology
2003–2004   
Tallinn University of Technology, M.Sc. study, Computer Engineering
1999–2003   
Tallinn University of Technology, B.Sc. study, Computer Engineering

Qualifications

Academic degrees
Sergei Devadze, Doctor's Degree, 2009, (sup) Raimund Ubar; Peeter Ellervee, Fault Simulation of Digital Systems, Tallinn University of Technology School of Information Technologies, Department of Computer Engineering Chair of Computer Systems Test and Verification.
 
 
Honours & awards
2007, Sergei Devadze, Scholarship of Estonian Information Technology Foundation
2006, Sergei Devadze, Scholarship of Estonian Information Technology Foundation
2005, Sergei Devadze, Scholarship of Estonian Information Technology Foundation
2004, Sergei Devadze, Scholarship of Estonian Information Technology Foundation
2003, Sergei Devadze, Estonian National Contest for Young Scientists at university level, I Prize
 
 
Fields of research
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.8. Electrical Engineering and Electronics; SPECIFICATION: Digital Testing, Fault Simulation of Digital Circuits, Synthesis of Complex Digital Systems
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.8. Electrical Engineering and Electronics; CERCS CLASSIFICATION: T171 Microelectronics ; SPECIFICATION: Advanced PCB test, microprocessor-based and FPGA-based board-level test methods
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.7. Telecommunications
 
 
Additional information
Principal investigator of ETF9423 project ("Chip-Embedded Instrumentation for Testing of Complex Electronic Systems", 1.01.2012−31.12.2015)

Completed projects

Dissertations under supervision

Supervised dissertations

Publications

1.1. Teadusartiklid, mis on kajastatud Web of Science andmebaasides Science Citation Index Expanded, Social Sciences Citation Index, Arts & Humanities Citation Index, Emerging Sources Citation Index ja/või andmebaasis Scopus (v.a. kogumikud)
 
Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; ter Braak, Timon D.; Devadze, Sergei; Fey, Goerschwin; Jenihhin, Maksim; Jutman, Artur; Kerkhoff, Hans G.; Könighofer, Robert; Koyfman, Shlomit; Malburg, Jan; Moran, Shiri; Raik, Jaan; Rauwerda, Gerard; Riener, Heinz; Röck, Franz; Shibin, Konstantin; Sunesen, Kim; Wan, Jinbo ... Zhao, Yong (2018). Designing Reliable Cyber-Physical Systems. Lecture Notes in Electrical Engineering, 454, 15−38.10.1007/978-3-319-62920-9_2.
 
Kõusaar, Jaak; Ubar, Raimund; Kostin, Sergei; Devadze, Sergei; Raik Jaan (2018). Exact Parallel Critical Path Fault Tracing to Speed-Up Fault Simulation in Sequential Circuits. International Journal of Microelectronics and Computer Science, 9 (1), 9−18.
 
Shibin, Konstantin; Jutman, Artur; Devadze, Sergei; Grabmann, Martin; Pricken, Robin (2017). Health Management for Self-Aware SoCs based on IEEE 1687 Infrastructure. IEEE Design and Test, 1−6.10.1109/MDAT.2017.2750902.
 
Aleksejev, I.; Jutman, A.; Devadze, S. (2017). Run-Time Reconfigurable Instruments for Advanced Board-Level Testing. IEEE Instrumentation & Measurement Magazine, 20 (4), 23−30.10.1109/MIM.2017.8006390.
 
Aleksejev Igor; Jutman Artur; Devadze Sergei; Shibin Konstantin (2016). Optimization of Boundary Scan Tests using FPGA-based Efficient Scan Architectures. Journal of Electronic Testing-Theory and Applications, 245−255.
 
Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J. (2015). Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocessors and Microsystems, 1−10.10.1016/j.micpro.2015.05.003.
 
Gorev, M.; Ubar, R.; Ellervee, P.; Devadze, S.; Raik, J.; Min, M. (2015). Functional Self-Test of High-Performance Pipe-Lined Signal Processing Architectures. Microprocessors and Microsystems, 39 (8), 909−918.10.1016/j.micpro.2014.11.002.
 
Ubar, Raimund; Kostin, Sergei; Kruus, Helena; Aarna, Margit; Devadze, Sergei (2014). Environment for Analysis of Functional Self-Test Quality in Digital Systems. Proceedings of the Estonian Academy of Sciences, 2 (63), 151−162.
 
Jutman, Artur; Devadze, Sergei; Shibin, Konstantin (2013). Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. IEEE Design & Test of Computers, 30 (5), 26−35.10.1109/MDAT.2013.2278535.
 
Raik, J.; Ubar, R.; Devadze, S.; Jutman, A (2005). Efficient single-pattern fault simulation on structurally synthesized bdds. Lecture Notes in Computer Science, 3463, 332−344.
1.2. Teadusartiklid teistes rahvusvahelistes teadusajakirjades, millel on registreeritud kood, rahvusvaheline toimetus, rahvusvahelise kolleegiumiga eelretsenseerimine, rahvusvaheline levik ning kättesaadavus ja avatus kaastöödele
 
Tsertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, Artjom (2014). In-System Programming of Non-Volatile Memories on Microprocessor-centric Boards. International Journal of Microelectronics and Computer Science, 5 (1), 25−34.
 
Tsertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, Artjom (2013). On In-System Programming of Non-volatile Memories (Extended). International Journal of Microelectronics and Computer Science, 4 (2), 72−78.
 
Shibin, Konstantin; Devadze, Sergei; Rosin, Vjatseslav; Jutman, Artur; Ubar, Raimund (2012). Open-Source JTAG Simulator Bundle for Labs. International Journal of Electronics and Telecommunications, 58 (3), 233−239. DOI: 10.2478/v10177-012-0032-4.
 
Ivask, Eero; Devadze, Sergei; Ubar, Raimund. (2011). Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Computing: Practice and Experience, Vol 12, 153-163.
 
Ivask, E.; Devadze, S.; Ubar, R. (2010). Distributed Approach for Parallel Exact Critical Path Tracing Fault Simulation. International Journal of Microelectronics and Computer Science, 1 (2), 165−174.
 
Ubar, R.; Jutman, A.; Kruus, M.; Orasson, E.; Devadze, S.; Wuttke, H.-D. (2007). Learning Digital Test and Diagnostics via Internet. International Journal of Online Engineering, 3 (1), 1−9.
2.3. Dissertatsioonide seerias ilmunud dissertatsioonid (v.a. käsikirjalised);
 
Devadze, Sergei (2009). Fault simulation of digital systems. (Doktoritöö, Tallinna Tehnikaülikool). Tallinn: Tallinn University of Technology Press.
3.1. Artiklid/peatükid lisas loetletud kirjastuste välja antud kogumikes (kaasa arvatud Web of Science Book Citation Index, Web of Science Conference Proceedings Citation Index, Scopus refereeritud kogumikud)
 
Ehrenberg H.; Odintsov S.; Devadze S.; Jutman A.; Aleksejev I.; Wenzel T.; (2019). Ways for board and system test to benefit from FPGA embedded synthetic instrumentation. Proc. of AUTOTESTCON’2019, Maryland, USA, 2019: AUTOTESTCON’2019, National Harbor, Maryland, USA, Aug 26-29, 2019. IEEE, 1−10. DOI: 10.1109/AUTOTESTCON43700.2019.8961057.
 
Jürimägi, Lembit; Ubar, Raimund; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Oyeniran, Adeboye. (2019). Application Specific True Critical Paths Identification in Sequential Circuits. 2019 25th IEEE International Symposium on On-Line Testing and Robust System Design: 25th IEEE International Symposium on On-Line Testing and Robust System Design Hotel Rodos Palace, Rhodes Island, Greece July 1-3, 2019. IEEE Computer Society, 1−6 [ilmumas].
 
Jürimagi, Lembit; Ubar, Raimund; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei (2018). Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Platja D'Aro, Hispaania, 2018. IEEE, 1−6.
 
Kõusaar, Jaak; Ubar, Raimund; Kostin, Sergei; Devadze, Sergei; Raik, Jaan (2018). Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. 25th International Conference Mixed Design of Integrated Circuits and Systems – MIXDES. Gdynia, Poland, June 21-23, 2018.. ieee, 305−310.
 
Tsertov, Anton; Jutman, Artur; Shibin, Konstantin; Devadze, Sergei (2018). IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring. 2018 IEEE AUTOTESTCON: AUTOTESTCON’2018, National Harbor, Maryland, USA, Sept 17-20, 2018. Piscataway, NJ, USA: IEEE, 1−9.10.1109/AUTEST.2018.8532559.
 
Odintsov, Sergei; Jutman, Artur; Devadze, Sergei; Aleksejev, Igor (2017). Embedded Instrumentation Toolbox for Screening Marginal Defects and Outliers for Production. Proc. of AUTOTESTCON’2017, Schaumburg, USA, Sept 11-14, 2017: AUTOTESTCON2017, Schaumburg, Illinois, USA, September 11-14, 2017. IEEE,.
 
Odintsov, Sergei; Jutman, Artur; Devadze, Sergei (2017). Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus. Proc of 48th IEEE International Test Conference (ITC’2017): IEEE International Test Conference (ITC’2017). Fort Worth, TX, USA, Oct 31 - Nov 2: IEEE,.
 
Shibin, Konstantin; Devadze, Sergei; Jutman, Artur (2016). On-line Fault Classification and Handling in IEEE1687 based Fault Management System for Complex SoCs. IEEE, 69−74.
 
Aleksejev, I.; Devadze, S.; Jutman, A. (2016). On Coverage of Timing Related Faults at Board Level. IEEE 21st European Test Symposium, Amsterdam, Netherlands, May 24 – May 27. IEEE, 1−2.10.1109/ETS.2016.7519295.
 
Aleksejev Igor; Jutman Artur; Devadze Sergei (2016). Run-Time Reconfigurable Instruments for Advanced Board-Level Testing. AUTOTESTCON 2016. USA: IEEE, 1−8.
 
Tšertov, Anton; Jutman, Artur; Devadze, Sergei; Sonza-Reorda, Matteo; Larsson, Erik; Ghani Zadegan, Farrokh; Cantoro, Riccardo; Montazeri, Mehrdad; Krenz-Baath, Rene (2016). A Suite of IEEE 1687 Benchmark Networks. Proc of 47th IEEE International Test Conference (ITC’2016): IEEE International Test Conference (ITC’2016), Fort Worth, TX, USA, Nov 15-17, 2016. IEEE, paper 6.1.
 
Jutman, Artur; Shibin, Konstantin; Devadze, Sergei (2016). Reliable Health Monitoring and Fault Management Infrastructure based on Embedded Instrumentation and IEEE 1687. Proc. of AUTOTESTCON’2016, Anaheim, USA, Sept 12-15, 2016: AUTOTESTCON’2016, Anaheim, USA, Sept 12-15, 2016. IEEE, 240−249.
 
Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; ter Braak, Timon; Devadze, Sergei; Fey, Goerschwin; Jenihhin, Maksim; Jutman, Artur; Kerkhoff, Hans G.; Koenighofer, Robert; Malburg, Jan; Moran, Shiri; Raik, Jaan; Rauwerda, Gerard; Riener, Heinz; Roeck, Franz; Shibin, Konstantin; Sunesen, Kim; Wan, Jinbo; Zhao, Yong (2016). Designing Reliable Cyber-Physical Systems Overview associated to the Special Session at FDL'16. NEW YORK: IEEE.
 
Ubar, Raimund; Kõusaar, Jaak; Gorev, Maksim; Devadze, Sergei (2015). Combinational Fault Simulation in Sequential Circuits. In: Proceedings of International Symposium on Circuits and Systems (2876−2879). Lisbon, Portugal, 24-27 May, 2015: IEEE Computer Society Press.10.1109/ISCAS.2015.7169287.
 
Gorev, Maksim; Ubar, Raimund; Devadze, Sergei (2015). Fault Simulation with Parallel Exact Critical Path Tracing in Multiple Core Environment. In: Proceedings of IEEE Conference on Design, Automation & Test in Europe – DATE-2015 (1−6).. Grenoble, France, 9-13 March, 2015: IEEE Computer Society Press.
 
Aleksejev, Igor; Jutman, Artur; Devadze, Sergei; Shibin, Konstantin (2015). Virtual Reconfigurable Scan-chains on FPGAs for Optimized Board Test. 16th IEEE Latin-American Test Symposium (LATS), Puerto Vallarta, Mexico, March 25 - 27, 2015. Puerto Vallarta, Mexico: IEEE, 1−6.10.1109/LATW.2015.7102411.
 
Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J. (2014). Critical Path Tracing based Simulation of Transition Delay Faults. 17th Euromicro Conference on Digital System Design, Verona, Italy, August 27-29, 2014. IEEE Computer Society.
 
Shibin, Konstantin; Jutman, Artur; Devadze, Sergei (2014). Asynchronous fault detection in IEEE P1687 instrument network. North Atlantic Test Workshop 2014. IEEE, 73−78.10.1109/NATW.2014.24.
 
Ghani Zadegan, Farrokh; Larsson, Erik; Jutman, Artur; Devadze, Sergei; Krenz-Baath, Rene (2014). Design, Verification and Application of IEEE 1687. Proceedings of 23rd Asian Test Symposium (ATS): Asian Test Symposium (ATS), Hangzhou, China, 2014. Hangzhou, China: IEEE, 93−100.10.1109/ATS.2014.28.
 
Gorev, M.; Ubar, R.; Ellervee, P.; Devadze, S.; Raik, J.; Min, M. (2013). At-Speed Self-Testing of High-Performance Pipe-Lined Processing Architectures. 2013 NORCHIP: 11–12 November, 2013 Vilnius, LITHUANIA: The 31st Norchip Conference, Vilnius, Lithuania, Nov. 2013. IEEE, 1−6.10.1109/NORCHIP.2013.6702000.
 
Tsertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, Artjom (2013). On In-System Programming of Non-volatile Memories. Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2013, Gdynia, Poland, June 20-22, 2013. IEEE, 408−413.
 
Kruus, H.; Ubar, R.; Ellervee, P.; Gorev, M.; Pesonen, V.; Devadze, S.; Orasson, E.; Brik, M.; Min, M.; Annus, P.; Kruus, M.; Meigas, K. (2012). A Benchmark Suite for Evaluating the Efficiency of Test Tools. BEC 2012 : 13th biennial Baltic Electronics Conference : proceedings of the 13th biennial Baltic Electronics Conference : Tallinn University of Technology, October 3-5, 2012, Tallinn, Estonia. Tallinn, 2012: The 13th Biennial Baltic Electronics Conference (BEC2012). Tallinn University of Technology, 85−88.
 
Jutman, Artur; Devadze, Sergei; Aleksejev, Igor; Wenzel, Thomas (2012). Embedded Synthetic Instruments for Board-Level Testing. IEEE 17th European Test Symposium, Annecy, France, May 28 – June 1. IEEE Computer Society,.
 
Aleksejev, Igor; Jutman, Artur; Devadze, Sergei; Odintsov, Sergei; Wenzel, Thomas (2012). FPGA-Based Synthetic Instrumentation for Board Test. 43th IEEE International Test Conference, Anaheim, CA, USA, Nov 4-9, 2012. IEEE Computer Society, 1−6.
 
Tsertov, Anton; Jutman, Artur; Devadze, Sergei; Ubar, Raimund (2011). Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Proceedings of 20th Asian Test Symposium (ATS): Asian Test Symposium (ATS), New Delhi, India, 2011. New Delhi, India, 532−538.10.1109/ATS.2011.79.
 
Jutman, Artur; Devadze, Sergei; Aleksejev, Jevgeni (2011). Invited paper: System-Wide Fault Management based on IEEE P1687 IJTAG. 6th IEEE Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, June 20-22, 2011 (1−6).. IEEE Computer Society.
 
Tsertov, Anton; Jurman, Artur; Ubar, Raimund; Devadze, Sergei (2011). Board-Level Modeling for PCB Testing. Proceedings of 14th Euromicro Conference on Digital System Design (1−6).. Oulu, Finland: IEEE Computer Society.
 
Ubar, Raimund; Mironov, Dmitri; Devadze, Sergei; Raik, Jaan; Jutman, Artur (2011). Digital Logic Simulation with Compressed BDDs. Proceedings of 2011 IEEE International Conference on Computer Science and Automation Engineering (CSAE), 3: 2011 IEEE International Conference on Computer Science and Automation Engineering, Shanghai, China, 10 - 12 Jun, 2011. IEEE Computer Society, 105−109.
 
Ubar, Raimund; Devadze, Sergei (2011). Fast Parallel Fault Reasoning in Digital Circuits. Design and Test Technology for Dependable Systems-on-chip (310−335).. USA, Hershey - New York: IGI Publishing.
 
Ivask, Eero; Devadze, Sergei; Ubar, Raimund (2010). Collaborative Distributed Fault Simulation for Digital Electronic Circuits. Intelligent Distributed Computing IV: 4th International Symposium on Intelligent Distributed Computing - IDC 2010, Tangier, Marocco, September 2010. Ed. Mohammad Essaaidi, Michele Malgeri, Costin Badica. Springer, 67−76. (Studies in Computational Intelligence).
 
Tsertov, Anton; Jutman, Artur; Devadze, Sergei. (2010). Testing Beyond the SoCs in a Lego Style. Proceedings of IEEE East-West Design & Test Symposium (EWDTS’10): IEEE East-West Design & Test Symposium (EWDTS’10). IEEE, 334−338.10.1109/EWDTS.2010.5742052.
 
Mironov, D.; Ubar, R.; Devadze, S.; Raik, J.; Jutman, A. (2010). Structurally Synthesized Multiple Input BDDs for Speeding up Logic-Level Simulation of Digital Circuits. Proc. of the 13th Euromicro Conference on Digital System Design – DSD’2010: 13th Euromicro Conference on Digital System Design – DSD’2010. Lille, France, Sept.1-3, 2010. IEEE, 658−663.10.1109/DSD.2010.27.
 
Ivask, Eero; Devadze, Sergei; Ubar, Raimund (2010). Distributed Approach for Parallel Exact Critical Path Tracing Fault Simulation. Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2010 : Wroclaw, Poland 24 - 26 June, 2010. Ed. Andrzej Napieralski. IEEE, 471−476.
 
Ivask, E.; Devadze, S.; Ubar, R. (2010). Collaborative Distributed Computing in the Field of Digital Electronics Testing. Information Technology for Balanced Automation Systems: BASYS 2010, Valencia, Spain, July 21-23. Springer, 145−152.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur. (2010). Parallel X-Fault Simulation with Critical Path Tracing Technique. In: Kathy Preas (Ed.). Proceedings of Design, Automation & Test in Europe : Dresden, Germany March 8-12, 2010 (879−884). . IEEE Computer Society Press.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur. (2010). Fast Fault Simulation for Extended Class of Faults in Scan-Path Circuits. Proc. of 5th IEEE Int. Symposium on Electronic Design, Test and Applications - DELTA 2010 (14−19). . Los Alamitos, California, USA: IEEE Computer Society.
 
Devadze, S.; Jutman, A.; Tsertov, A.; Ubar, R. (2009). Microprocessor Modeling for Board Level Test Access Automation. Proc. of 10th IEEE Workshop on RTL and High Level Testing: 10th IEEE Workshop on RTL and High Level Testing, Hong Kong, Nov. 27-28, 2009. IEEE, 154−159.
 
Devadze, S.; Jutman, A.; Aleksejev, I.; Ubar, R. (2009). Fast Extended Test Access via JTAG and FPGAs. Proc. of 40th International Test Conference - ITC’2009: 40th International Test Conference - ITC’2009, Austin, Texas, Nov. 1-6, 2009. paper 2.3−pp- 1-7.
 
Devadze, Sergei; Jutman, Artur; Aleksejev, Igor; Ubar, Raimund (2009). Turning JTAG inside out for fast extended test access. 10th IEEE Latin American Test Workshop, 2-5 March, 2009, Buzios, Brazil. Buzios, Brazil: IEEE, 1−6.
 
Devadze, Sergei; Ubar, Raimund; Raik, Jaan; Jutman, Artur (2009). Parallel Exact Critical Path Tracing Fault Simulation with Reduced Memory Requirements. In: 4th IEEE Int. Conf. on Design and Technology of Integrated Systems in Nanoscale Era – DTIS’09, Cairo, Egypt, April 6-7, 2009 (155−160). . IEEE Computer Society Press.
 
Ferreira, J.M.; Sousa, E.; Ubar, R.; Jutman, A.; Devadze, S. (2009). Remote boundary-scan testing through micro-webservers. Proc. of 3rd IEEE International Conference on e-Learning in Industrial Electronics - ICELIE'2009: 3rd IEEE International Conference on e-Learning in Industrial Electronics - ICELIE'2009. Portugal, Porto,.
 
Devadze, Sergei; Jutman, Artur; Tsertov, Anton; Instenberg, Martin; Ubar, Raimund (2008). Microprocessor-based System Test using Debug Interface. In: 26th IEEE NORCHIP Conference (40.10).. IEEE.
 
Devadze, Sergei (2008). Software Environment for Synthesis of Testable FSM through Decomposition. IEEE 26th International Conference on Microelectronics (MIEL 2008), Nis, Serbia. 433−436.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur (2008). Parallel Fault Backtracing for Calculation of Fault Coverage. The 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008). IEEE Computer Society Press, 667−672.
 
Ubar, Raimund; Devadze, Sergei; Jenihhin, Maksim; Raik, Jaan; Jervan, Gert; Ellervee, Peeter (2008). Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. IEEE International Symposium on Electronic Design, Test and Applications (DELTA), January 23 - 25, 2008, Hongkong. IEEE Computer Society Press, 222−227.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur (2007). Ultra Fast Parallel Fault Analysis on Structural BDDs. In: Proceedings 12th IEEE European Test Symposium – ETS 2007 (131−136). . IEEE Computer Society Press.
 
Sudnitson, Alexander; Devadze, Sergei (2007). Web-Based Computer Aided Design Support of Finite State Machine Additive Decomposition for Low Power. 5th IEEE East-West Design & Test International Symposium. 494−498.
 
Devadze, Sergei; Raik, Jaan; Jutman, Artur; Ubar, Raimund. (2006). Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using Structurally Synthesized BDDs. Proceedings of 7th IEEE Latin-American Test Workshop (97−102). . IEEE Computer Society Press.
 
"Devadze, Sergei;Sudnitsõn, Aleksander" (2005). FSM decomposition software for education and research. Proc. IEEE EUROCON 2005 International Conference on Computer as a tool : Belgrade, Serbia & Montenegro. Belgrad: TTY puuduv kirjastus, 839−842.
 
Devadze, Sergei; Fomina, Jelena; Kruus, Margus; Sudnitsõn, Aleksander (2003). Web-based system for sequential machines decomposition. In: EUROCON 2003. Computer as a Tool. (57−61).. [S. l.]: IEEE.
 
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2002). Java Technology Based Training System for Teaching Digital Design and Test. Proc. of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002: 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002. 283−286.
3.2. Artiklid/peatükid lisas mitte loetletud kirjastuste välja antud kogumikes
 
Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; ter Braak, Timon; Devadze, Sergei; Fey, Goerschwin; Jenihhin, Maksim; Jutman, Artur; Kerkhoff, Hans G.; Könighofer, Robert; Malburg, Jan; Moran, Shiri; Raik, Jaan; Rauwerda, Gerard; Riener, Heinz; Röck, Franz; Shibin, Konstantin; Sunesen, Kim; Wan, Jinbo; Zhao, Yong (2016). Designing Reliable Cyber-Physical Systems. In: ECSI FDL 2016 Forum on specification & Design Languages, September 14-16, 2016 Bremen, Germany (1−8). ECSI.
 
Bedoya, C. F.; Cela, J. M.; Fouz, M. C.; Francia, D.; Navarro, A.; Puerta, J.; Sastre, J.; Redondo, I.; Beni, N; Szillasi, Z.; Balbi, G.; Baldanza, C.; Cafaro, V.; Cavallo, F.R.; Codispoti, G.; Dallavalle, G.M.; Giordano, V.; Guiducci, L; Masetti, G.; Siroli, G.P. ... Devadze, S. (2015). CMS Drift Tubes Sector Collector Relocation Phase 1 Upgrade. In: The CMS Experiment Detector Note (1−41).. Geneva, Switzerland: CERN.
 
Ubar, Raimund; Jutman, Artur; Raik, Jaan; Devadze, Sergei; Aleksejev, Igor; Chepurov, Anton; Chertov, Anton; Kostin, Sergei; Orasson, Elmet; Wuttke, H.-D. (2010). E-Learning Environment for WEB-Based Study of Testing. Proc. of the 8th European Workshop on Microelectronics Education - EWME 2010: 8th European Workshop on Microelectronics Education - EWME 2010. Saksamaa, Darmstadt, 47−52.
 
Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur (2007). Parallel Fault Backtracing for Calculation of Fault Coverage. In: International Conference on Microelectronics, Devices and Materials and the Workshop on Electronic Testing (MIDEM'07) Proceedings (165−170). . Slovenia: MIDEM Society for Microelectronics, Electronic Components and Materials.
 
Ubar, Raimund; Jutman, Artur; Devadze, Sergei; Wuttke, Hans-Dietrich (2007). Bringing Research Issues into Lab Scenarios on the Example of SOC Testing. In: ICEE Proceedings (N/A).. University of Coimbra.
 
Devadze, Sergei; Kruus, Margus; Sudnitsõn, Aleksander (2001). Web-based software implementation of finite state machine decomposition for design and education. Proc. International Conference on Computer Systems and Technologies : CompSys'2001 : Sofia, Bulgaria, 2001.
3.4. Artiklid/ettekanded, mis on avaldatud valdkonda 3.1. mittekuuluvates konverentsikogumikes
 
Jutman, Artur; Devadze, Sergei; Shibin, Konstantin (2016). Synchronization, Calibration and Triggering of IEEE 1687 Embedded Instruments. Proc. of the 17th Workshop on RTL and High Level Testing (WRTLT’2016): 17th Workshop on RTL and High Level Testing (WRTLT’2016), Nov. 24-25, 2016, Hiroshima, Japan. IEEE, 1−6.
 
Shibin, Konstantin; Jutman, Artur; Devadze, Sergei (2013). Fault Management Instrumentation Network based on IEEE P1687 IJTAG. 18th IEEE European Test Symposium (PhD student work-in-progress Papers), May 27-31, 2013. IEEE Computer Society,.
 
Shibin, Konstantin; Aleksejev, Igor; Jutman, Artur; Devadze, Sergei (2012). IEEE P1687 IJTAG demonstrator on FPGA. DATE 2012 University Booth: Design Automation and Test in Europe, Dresden, Germany, March 12-16. Association for Computing Machinery (ACM),.
 
Pleskacz, Witold; Jutman, Artur; Ubar, Raimund; Devadze, Sergei (2007). DefSim – the defective IC. DATE 2007 University Booth: Design Automation and Test in Europe, Nice, France, April 16-20, 2007. Ed. Rudy Lauwereins, Jan Madsen. ACM, s96.
 
Sudnitson, Alexander; Sergei, Devadze (2006). Computer Aided Design Support of FSM Multiplicative Decomposition. IEEE East-West Design&Test International Workshop (EWDTW'06), Sochi, Russia. 241−246.
 
Devadze, S.; Gorjachev, R.; Jutman, A.; Orasson, E.; Rosin, V.; Ubar, R. (2003). E-Learning Tools for Digital Test. Distance Learning – Educational Environment of the XXI Century: Minsk, Nov. 13-15, 2003. 336−342.
 
Devadze, S.; Jutman, A.; Kruus, M.; Sudnitson, A.; Ubar, R. (2002). Web Based Tools for Synthesis and Testing of Digital Devices. Proc. International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002: International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002. I.91−I.96.
 
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R. (2002). Web-based training system for teaching basics of RT-level Digital Design, Test, and Design for Test. Proc. of 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002: 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002. 699−704.
 
Devadze, S.; Jutman, A.; Sudnitson, A.; Ubar, R.; Wuttke, H.-D. (2002). Teaching Digital RT-Level Self-Test using a Java Applet. 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002. 322−328.
3.5. Artiklid/ettekanded, mis on avaldatud kohalikes konverentsikogumikes
 
Shibin, Konstantin; Jutman, Artur; Devadze, Sergei (2012). System-Wide Fault Management based on IEEE P1687 IJTAG. The Fourth Annual Conference of the National Doctoral School in Information and Communication Technologies, October 3 – 5, 2012, Laulasmaa SPA hotel.
 
Devadze, Sergei; Ubar, Raimund (2007). Parallel Fault Analysis on Structurally Synthesized BDDs. Teine IKTDK aastakonverents, Viinistu, 2007. Estonia, 47−50.
 
Devadze, Sergei (2006). Efficient Fault Simulation Method on Structurally Synthesized BDDs. Esimene IKTDK aastakonverents. Estonia, 123−126.
 
Devadze, Sergei (2003). Web-Based Training System for Teaching Digital Design and Test. Proc. of 7th International Student Conference on Electrical Engineering, (POSTER2003): 7th International Student Conference on Electrical Engineering, (POSTER2003). Prague, Czech Republic, IC6.

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ProgrammLiikNumberNimiProjekti algusProjekti lõppVastutav täitjaAsutusFinantseerijapoolne rahastamine
PRGPRG780CMS eksperimendi ettevalmistamine kõrge heledusega tööperioodil läbi triggeri uuenduste01.01.202031.12.2024Mario KadastikKeemilise ja Bioloogilise Füüsika Instituut514 250,00 EUR
1.2.2.1.11.E!5568COMBOARD - FPGA-Based Test Acceleration Methodology for Complex Electronic Boards01.04.201131.03.2013Artur JutmanTestonica Lab OÜ133 110,00 EUR (kogurahastus 553 966,00 EUR)
1.2.2.1.248613DIAMOND - Diagnosis, Error Modelling and Correction for Reliable Systems Design01.01.201031.12.2012Artur JutmanTallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut; Testonica Lab OÜ594 214,00 EUR (kogurahastus 3 863 697,00 EUR)
ETFETF5649Digitaalskeemide defekt-orienteeritud diagnostika01.01.200331.12.2006Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond40 819,99 EUR
SFSF0142508s03Digitaalsüsteemide disain ja test01.01.200331.12.2007Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond658 321,94 EUR
1.2.2.1.619871Elektroonikasüsteemide testi-instrumendid tehnoloogia vananemise vältimiseks ja diagnoosimatute rikete avastamiseks (BASTION) 01.01.201430.04.2017Artur JutmanTestonica Lab OÜ; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut3 442 000,00 EUR
MUUELIKO 2.2Hajus- ja sardsüsteemide testimine, verifitseerimine ning diagnostika01.07.200930.06.2015Jüri VainELIKO Tehnoloogia Arenduskeskus OÜ1 826 248,00 EUR
1.2.2.1.644905IMMORTAL – Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems01.03.201528.02.2018Artur JutmanTestonica Lab OÜ; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut305 512,50 EUR (kogurahastus 3 996 652,50 EUR)
TKTAR8077Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus CEBE07.07.200831.08.2015Raimund UbarTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut2 066 263,60 EUR
ETFETF7483Isediagnoosivad digitaalsüsteemid01.01.200831.12.2011Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond55 414,27 EUR
ETFETF5910Isetestivad digitaalsüsteemid01.01.200431.12.2007Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond51 822,58 EUR
ETFETF9423Kiibisisesed instrumendid elektroonikasüsteemide testimiseks01.01.201231.12.2015Sergei DevadzeTallinna Tehnikaülikool, Infotehnoloogia teaduskond46 440,00 EUR
1.2.5.4000124897 (4000124897/18/NL/CBi)On-Chip Health Monitoring and Fault Management for SoC Health-Awareness in Space Missions01.08.201829.02.2020Artur JutmanTestonica Lab OÜ199 908,00 EUR (kogurahastus 199 908,00 EUR)
ETFETF7894Süsteemitesti meetodid keerukatele trükkplaatidele01.01.200931.12.2012Artur JutmanTallinna Tehnikaülikool, Infotehnoloogia teaduskond44 999,60 EUR
MUU489FTehnoloogia arenduskeskus ELIKO projekt 1.4 Digitaalsüsteemide struktuurigeneraator01.11.200431.10.2007Jaan RaikTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 124 627,71 EUR
MUULep9007Tehnoloogia arenduskeskus ELIKO projekt 2.2 Sardsüsteemide test, verifitseerimine ja silumine01.09.200830.06.2009Jaan RaikTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool 8 500,25 EUR
SFSF0140041s08Töökindlate sardsüsteemide disain01.01.200831.12.2013Raimund UbarTallinna Tehnikaülikool, Infotehnoloogia teaduskond1 504 530,37 EUR
IUTIUT19-1Usaldusväärsed mitmetuumalised arvutisüsteemid01.01.201431.12.2019Jaan RaikTallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutisüsteemide instituut1 572 000,00 EUR
MUUVFP382Usaldusväärsete süsteemide kompetentsikeskus01.03.200929.02.2012Gert JervanTallinna Tehnikaülikool; Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut983 099,97 EUR