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Anton Karputkin

https://www.etis.ee/CV/Anton_Karputkin/est
10.10.1983
55687493
akarputkin@gmail.com

Teenistuskäik

Töökohad ja ametid
01.10.2012–31.08.2016   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut, Arvutisüsteemide diagnostika ja verifitseerimise õppetool , Teadur (1,00)
2008–2012   
Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, doktorant (1,00)
 
 
Haridustee
2008–2012   
Tallinna Tehnika Ülikooli Infotehnoloogia Teaduskond (Doktoriõpe)
2005–2008   
Tartu Ülikooli Matemaatika-Informaatika Teaduskond (Magistriõpe)
2002–2005   
Tartu Ülikooli Matemaatika-Informaatika Teaduskond (Bakaureuseõpe)
1999–2002   
Tallinna Tõnismäe Reaalkool
1990–1999   
Lasnamäe Vene Gümnaasium

Kvalifikatsioon

Teaduskraadid
Anton Karputkin, doktorikraad, 2012, (juh) Raimund Ubar; Jaan Raik; Mati Tombak, Formal verification and error correction on high-level decision diagrams (Formaalne verifitseerimine ja vigade parandamine kõrgtasemelistel otsustusdiagrammidel), Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut.
Anton Karputkin, magistrikraad, 2008, (juh) Ahti Peder, Translation and solving system for boolean formulae with metavariables (Metamuutujatega loogikavalemite transleerimise ja lahendamise süsteem), Tartu Ülikool.
 
 
Teadustöö põhisuunad
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.7. Info- ja kommunikatsioonitehnoloogia; TÄPSUSTUS: Mitmevalentne loogika

Lõppenud projektid

Publikatsioonid

Klass
Aasta
Publikatsioon
 
1.1.
2012
Viilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund; Fujiwara, Hideo (2012). Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. Journal of Electronic Testing-Theory and Applications, 28 (4), 511−521.
2.3.
2012
Karputkin, Anton (2012). Formal Verification and Error Correction on High-Level Decision Diagrams. (Tallinna Tehnika Ülikool). TTU Press.
3.1.
2012
Karputkin, A.; Ubar, R.; Tombak, M.; Raik, J. (2012). Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams. 13th International Symposium on Quality Electronic Design (ISQED), 2012: International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 19-21.03.2012. IEEE, 686−693. DOI: 10.1109/ISQED.2012.6187566.
3.1.
2012
Raik, J.; Drenkhan, T.; Jenihhin, M.; Viilukas, T.; Karputkin, A.; Tšepurov, A.; Ubar, R. (2012). Generating Directed Tests for C Programs using RTL ATPG. Proceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12): IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12), Niigata, Japan, November 22-23, 2012. , 1−6.
3.1.
2011
Karputkin, A.; Ubar, R.; Tombak, M.; Raik, J. (2011). Interactive Presentation Abstract: Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams. Conference Proceedings: IEEE International High Level Design Validation and Test Workshop, Napa Valley, Nov. 9-11, 2011. IEEE Computer Society, 83. DOI: 10.1109/HLDVT.2011.6113980.
3.1.
2011
Karputkin, Anton; Ubar, Raimund; Tombak, Mati; Raik, Jaan (2011). Probabilistic Equivalence Checking Based on High-Level Decision Diagrams. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 13-15, 2011, Cottbus, Germany. IEEE Computer Society Press, 423−428.
3.5.
2011
Karputkin, Anton (2011). High Level Decision Diagrams and Characteristic Polynomials. 5th Annual Conference of the National Doctoral School in Information and Communication Technologies, Nelijärve, 25.-26.11.
1.2.
2010
Karputkin, A.; Ubar, R.; Raik, J.; Tombak, M. (2010). Canonical Representation of High Level Decision Diagrams. Estonian Journal of Engineering, 16 (1), 39−55.
3.1.
2009
Ubar, R.; Raik, J.; Karputkin, A.; Tombak, M. (2009). Synthesis of High-level Decision Diagrams for Functional Test Pattern Generation. Proceedings of the 16th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2009 : Lodz, Poland 25 - 27 June, 2009. Ed. Andrzej Napieralski. Lodz: IEEE, 519−524.
26.10.2020

Anton Karputkin

https://www.etis.ee/CV/Anton_Karputkin/eng
10.10.1983
55687493
akarputkin@gmail.com

Career

Institutions and positions
01.10.2012–31.08.2016   
Tallinn University of Technology , School of Information Technologies, Department of Computer Engineering , Chair of Computer Systems Test and Verification, Researcher (1,00)
2008–2012   
Tallinn University of Technology , School of Information Technologies, PhD student (1,00)
 
 
Education
2008–2012   
Tallinn University of Technology, Faculty of Information Technology (PhD Studies)
2005–2008   
University of Tartu, Faculty of Mathematics and Computer Science (Master studies)
2002–2005   
University of Tartu, Faculty of Mathematics and Computer Science (Bachelor studies)
1999–2002   
Tallinna Tõnismäe Reaalkool
1990–1999   
Lasnamäe Vene Gümnaasium

Qualifications

Academic degrees
Anton Karputkin, Doctor's Degree, 2012, (sup) Raimund Ubar; Jaan Raik; Mati Tombak, Formal verification and error correction on high-level decision diagrams, Tallinn University of Technology School of Information Technologies, Department of Computer Engineering.
Anton Karputkin, Master's Degree, 2008, (sup) Ahti Peder, Translation and solving system for boolean formulae with metavariables, University of Tartu.
 
 
Fields of research
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.7. Telecommunications; SPECIFICATION: Multi-Valued Logic
 
 

Completed projects

Publications

Category
Year
Publication
 
1.1.
2012
Viilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund; Fujiwara, Hideo (2012). Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. Journal of Electronic Testing-Theory and Applications, 28 (4), 511−521.
2.3.
2012
Karputkin, Anton (2012). Formal Verification and Error Correction on High-Level Decision Diagrams. (Tallinna Tehnika Ülikool). TTU Press.
3.1.
2012
Karputkin, A.; Ubar, R.; Tombak, M.; Raik, J. (2012). Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams. 13th International Symposium on Quality Electronic Design (ISQED), 2012: International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 19-21.03.2012. IEEE, 686−693. DOI: 10.1109/ISQED.2012.6187566.
3.1.
2012
Raik, J.; Drenkhan, T.; Jenihhin, M.; Viilukas, T.; Karputkin, A.; Tšepurov, A.; Ubar, R. (2012). Generating Directed Tests for C Programs using RTL ATPG. Proceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12): IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12), Niigata, Japan, November 22-23, 2012. , 1−6.
3.1.
2011
Karputkin, A.; Ubar, R.; Tombak, M.; Raik, J. (2011). Interactive Presentation Abstract: Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams. Conference Proceedings: IEEE International High Level Design Validation and Test Workshop, Napa Valley, Nov. 9-11, 2011. IEEE Computer Society, 83. DOI: 10.1109/HLDVT.2011.6113980.
3.1.
2011
Karputkin, Anton; Ubar, Raimund; Tombak, Mati; Raik, Jaan (2011). Probabilistic Equivalence Checking Based on High-Level Decision Diagrams. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 13-15, 2011, Cottbus, Germany. IEEE Computer Society Press, 423−428.
3.5.
2011
Karputkin, Anton (2011). High Level Decision Diagrams and Characteristic Polynomials. 5th Annual Conference of the National Doctoral School in Information and Communication Technologies, Nelijärve, 25.-26.11.
1.2.
2010
Karputkin, A.; Ubar, R.; Raik, J.; Tombak, M. (2010). Canonical Representation of High Level Decision Diagrams. Estonian Journal of Engineering, 16 (1), 39−55.
3.1.
2009
Ubar, R.; Raik, J.; Karputkin, A.; Tombak, M. (2009). Synthesis of High-level Decision Diagrams for Functional Test Pattern Generation. Proceedings of the 16th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2009 : Lodz, Poland 25 - 27 June, 2009. Ed. Andrzej Napieralski. Lodz: IEEE, 519−524.
26.10.2020