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Saif Abrar Syed

https://www.etis.ee/CV/Saif Abrar_Syed/est
18.12.1977
+91 9886512327
syedsaifabrar@gmail.com
ESL engineer and professional

Teenistuskäik

Töökohad ja ametid
01.01.2012–...   
IBM
01.01.2010–31.12.2012   
Intel
01.01.2000–31.12.2010   
Philips/NXP
 
 
Haridustee
1998–2000   
Master's degree
1994–1998   
Bachelor's degree
 
 
Teadusorganisatsiooniline ja -administratiivne tegevus
2012−...   
Team lead
2010−2012   
Project lead

Kvalifikatsioon

Teaduskraadid
Saif Abrar Syed, doktorikraad, 2016, (juh) Maksim Jenihhin; Jaan Raik, Comprehensive Abstraction of VHDL RTL Cores to ESL SystemC (Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteks), Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut.
Saif Abrar Syed, magistrikraad (teaduskraad), 2000, (juh) Prof Anshul Kumar, High-level model for Co-simulation and Communication in Heterogeneous Embedded Platform (Kõrgetasemeline mudel Co-simulatsioon ja kommunikatsioon Heterogeenne Embedded platform), Indian Institute of Technology (Delhi).
 
 
Teadustöö põhisuunad
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.6. Arvutiteadused; CERCS KLASSIFIKAATOR: T120 Süsteemitehnoloogia, arvutitehnoloogia

Lõppenud projektid

Publikatsioonid

Klass
Aasta
Publikatsioon
 
3.1.
2014
Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan. (2014). Abstraction of clock interface for conversion of RTL VHDL to SystemC. IEEE International Advance Computing Conference (IACC), Gurgaon, Feb-2014.. IEEE, 50−55.10.1109/IAdCC.2014.6779293.
3.2.
2014
Jenihhin, Maksim; Tihhomirov, Valentin; Syed, Saif Abrar; Raik, Jaan; Bartsch, Günter (2014). zamiaCAD: Understand, Develop and Debug Hardware Designs. 1st Workshop on Design Automation for Understanding Hardware Designs (DuHDE), Friday Workshop at DATE 2014, Dresden, Germany, March 28, 2014. University of Bremen, Institute of Technology and Education, 1−6.
3.1.
2013
Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2013). Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC. 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Karlovy Vary, Czech Republic, April 8-10, 2013. 112−115.
3.1.
2013
Syed, Saif Abrar; Shyam, Kiran A.; Jenihhin, Maksim; Raik, Jaan; Babu, C. (2013). Performance Analysis of Cosimulating Processor Core in VHDL and SystemC. Proc. of 2nd IEEE International Conference on Advances in Computing, Communications & Informatics: 2nd IEEE International Conference on Advances in Computing, Communications & Informatics, Mysore, India, 22–25 August, 2013. 1−6.
3.4.
2013
Tihhomirov, Valentin; Tšepurov, Anton; Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2013). VHDL Design Debug Framework Based on zamiaCAD. DATE 2013 University Booth: Design Automation and Test in Europe, Grenoble, France, March 18-22, 2013. 1−1.
5.2.
2013
Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2013). Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL. IP-SoC 2013 (IP Based Electronic System Conference), Grenoble, France, 6-7 Nov 2013.
3.4.
2012
Syed, S. A.; Jenihhin, M.; Raik, J. (2012). Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC. IP-SOC 2012 Conference, Grenoble, France, December 4-5, 2012.
3.4.
2012
Chepurov, Anton; Tihhomirov, Valentin; Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2012). Applications of the Open Source HW Design Framework zamiaCAD. DATE 2012 University Booth: Design Automation and Test in Europe, Dresden, Germany, March 12-16, 2012. 1−1.
18.04.2019

Saif Abrar Syed

https://www.etis.ee/CV/Saif Abrar_Syed/eng
18.12.1977
+91 9886512327
syedsaifabrar@gmail.com
ESL engineer and professional

Career

Institutions and positions
01.01.2012–...   
IBM
01.01.2010–31.12.2012   
Intel
01.01.2000–31.12.2010   
Philips/NXP
 
 
Education
1998–2000   
Master's degree
1994–1998   
Bachelor's degree
 
 
R&D related managerial and administrative work
2012−...   
Team lead
2010−2012   
Project lead

Qualifications

Academic degrees
Saif Abrar Syed, Doctor's Degree, 2016, (sup) Maksim Jenihhin; Jaan Raik, Comprehensive Abstraction of VHDL RTL Cores to ESL SystemC, Tallinn University of Technology School of Information Technologies, Department of Computer Engineering.
Saif Abrar Syed, Research Master's Degree, 2000, (sup) Prof Anshul Kumar, High-level model for Co-simulation and Communication in Heterogeneous Embedded Platform, Indian Institute of Technology (Delhi).
 
 
Fields of research
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.6. Computer Sciences; CERCS CLASSIFICATION: T120 Systems engineering, computer technology
 
 

Completed projects

Publications

Category
Year
Publication
 
3.1.
2014
Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan. (2014). Abstraction of clock interface for conversion of RTL VHDL to SystemC. IEEE International Advance Computing Conference (IACC), Gurgaon, Feb-2014.. IEEE, 50−55.10.1109/IAdCC.2014.6779293.
3.2.
2014
Jenihhin, Maksim; Tihhomirov, Valentin; Syed, Saif Abrar; Raik, Jaan; Bartsch, Günter (2014). zamiaCAD: Understand, Develop and Debug Hardware Designs. 1st Workshop on Design Automation for Understanding Hardware Designs (DuHDE), Friday Workshop at DATE 2014, Dresden, Germany, March 28, 2014. University of Bremen, Institute of Technology and Education, 1−6.
3.1.
2013
Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2013). Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC. 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Karlovy Vary, Czech Republic, April 8-10, 2013. 112−115.
3.1.
2013
Syed, Saif Abrar; Shyam, Kiran A.; Jenihhin, Maksim; Raik, Jaan; Babu, C. (2013). Performance Analysis of Cosimulating Processor Core in VHDL and SystemC. Proc. of 2nd IEEE International Conference on Advances in Computing, Communications & Informatics: 2nd IEEE International Conference on Advances in Computing, Communications & Informatics, Mysore, India, 22–25 August, 2013. 1−6.
3.4.
2013
Tihhomirov, Valentin; Tšepurov, Anton; Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2013). VHDL Design Debug Framework Based on zamiaCAD. DATE 2013 University Booth: Design Automation and Test in Europe, Grenoble, France, March 18-22, 2013. 1−1.
5.2.
2013
Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2013). Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL. IP-SoC 2013 (IP Based Electronic System Conference), Grenoble, France, 6-7 Nov 2013.
3.4.
2012
Syed, S. A.; Jenihhin, M.; Raik, J. (2012). Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC. IP-SOC 2012 Conference, Grenoble, France, December 4-5, 2012.
3.4.
2012
Chepurov, Anton; Tihhomirov, Valentin; Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan (2012). Applications of the Open Source HW Design Framework zamiaCAD. DATE 2012 University Booth: Design Automation and Test in Europe, Dresden, Germany, March 12-16, 2012. 1−1.
18.04.2019