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Taavi Viilukas

https://www.etis.ee/CV/Taavi_Viilukas/est

Teenistuskäik

Haridustee
2006–2012   
Tallinna Tehnikaülikool, informaatika, doktorikraad
2004–2006   
Tallinna Tehnikaülikool, arvuti- ja süsteemitehnika eriala, magistrikraad
1999–2004   
Tallinna Tehnikaülikool, arvutisüsteemide eriala, diplom
1996–1999   
Tallinna Laagna Gümnaasium
 
 
Loometöö
Ajakirjas A & A avaldatud artikkel: "Beowulf - kobararvuti", nr. 3, 2005

Kvalifikatsioon

Teaduskraadid
Taavi Viilukas, doktorikraad, 2012, (juh) Jaan Raik, Mudelikontrolli meetod kõrgtaseme otsustusdiagrammidel, Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut.
Taavi Viilukas, magistrikraad (teaduskraad), 2006, (juh) Jaan Raik, Rikete levitamise analüüs ja parandus hierarhilises testigeneraatoris, Tallinna Tehnikaülikool, Infotehnoloogia teaduskond, Arvutitehnika instituut.
 
 
Teadustöö põhisuunad
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.7. Info- ja kommunikatsioonitehnoloogia
ETIS KLASSIFIKAATOR: 4. Loodusteadused ja tehnika; 4.6. Arvutiteadused

Publikatsioonid

Klass
Aasta
Publikatsioon
 
1.2.
2011
Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund; Viilukas, Taavi; Fujiwara, Hideo (2011). An Approach for Verification Assertions Reuse in RTL Test Pattern Generation. J. of Shanghai Normal University (Natural Sciences), Vol. 39, 441−447.
3.1.
2011
Jenihhin, M.; Raik, J.; Fujiwara, H.; Ubar, R.; Viilukas, T. (2011). An Approach for Verification Assertions Reuse in RTL Test Pattern Generation. Proceedings of the IEEE 11th Workshop on RTL and High Level Testing (WRTLT'10): IEEE 11th Workshop on RTL and High Level Testing (WRTLT'10), Shanghai, China, December 5-6, 2010,. 1−6.
3.1.
2011
Viilukas, Taavi; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund; Baranov, Samary (2011). Automated Test Bench Generation for High-Level Synthesis flow ABELITE. Proceedings of IEEE East-West Design & Test Symposium 2011 (1−6).. Sevastopol, Ukraine: IEEE Computer Society.
3.1.
2011
Raik, J; Rannaste, A; Jenihhin, M; Viilukas, T; Fujiwara, H; Ubar, R (2011). Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. Proceedings of IEEE European Test Symposium, (1−6).. IEEE Computer Society Press.
3.1.
2010
Viilukas, Taavi; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund; Krivenko, Anna (2010). Constraint-based Test Pattern Generation at the Register-Transfer Level. Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 14–16, 2010 Vienna, Austria. IEEE, 352−357.10.1109/DDECS.2010.5491752.
1.1.
2008
Raik, J.; Ubar, R.; Viilukas, T.; Jenihhin, M. (2008). Mixed hierarchical-functional fault models for targeting sequential cores. Journal of Systems Architecture, 54, 465−477.
3.1.
2008
Chepurov, Anton; Di Guglielmo, Giuseppe; Fummi, Franco; Pravadelli, Graziano; Raik, Jaan; Ubar, Raimund; Viilukas, Taavi (2008). Automatic Generation of EFSMs and HLDDs for Functional ATPG. In: 11th Biennial Baltic Electronics Conference (143−146). . IEEE.
3.1.
2006
Raik, Jaan; Ubar, Raimund; Viilukas, Taavi (2006). High-Level Decision Diagram based Fault Models for Targeting FSMs. Proceedings of the 9th IEEE Euromicro Conference on Digital Systems Design: DSD2006, Cavtat, Aug. 31- Sept. 2, 2006. IEEE Computer Society Press, 353−358.
25.11.2020

Taavi Viilukas

https://www.etis.ee/CV/Taavi_Viilukas/eng
+372 620 2252

Career

Institutions and positions
01.01.2006–...   
Termnet Eesti OY, systemadministrator
01.01.2004–31.12.2008   
Aero Airlines AS, IT specialist
01.01.2002–31.12.2004   
Public Service Academy, lecture
01.01.2002–31.12.2002   
Siemens Electroservices AS, graphic-designer
01.01.2001–31.12.2004   
Public Service Academy, specialist
01.01.1998–31.12.1998   
Rocca al Mare tivoli, game leader
 
 
Education
2004–2006   
Tallinn University of Technology, informatics, master degree
1999–2004   
Tallinn University of Technology, computer-system, diploma
1996–1999   
Laagna Highschool

Qualifications

Academic degrees
Taavi Viilukas, Doctor's Degree, 2012, (sup) Jaan Raik, Mudelikontrolli meetod kõrgtaseme otsustusdiagrammidel (Model-checking methods using high-level decision diagrams), Tallinn University of Technology School of Information Technologies, Department of Computer Engineering.
Taavi Viilukas, Research Master's Degree, 2006, (sup) Jaan Raik, Rikete levitamise analüüs ja parandus hierarhilises testigeneraatoris (Fault propagation methods in hierarchical test pattern generation), Tallinn University of Technology School of Information Technologies, Department of Computer Engineering.
 
 
Fields of research
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.7. Telecommunications
ETIS CLASSIFICATION: 4. Natural Sciences and Engineering; 4.6. Computer Sciences

Publications

Category
Year
Publication
 
1.2.
2011
Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund; Viilukas, Taavi; Fujiwara, Hideo (2011). An Approach for Verification Assertions Reuse in RTL Test Pattern Generation. J. of Shanghai Normal University (Natural Sciences), Vol. 39, 441−447.
3.1.
2011
Jenihhin, M.; Raik, J.; Fujiwara, H.; Ubar, R.; Viilukas, T. (2011). An Approach for Verification Assertions Reuse in RTL Test Pattern Generation. Proceedings of the IEEE 11th Workshop on RTL and High Level Testing (WRTLT'10): IEEE 11th Workshop on RTL and High Level Testing (WRTLT'10), Shanghai, China, December 5-6, 2010,. 1−6.
3.1.
2011
Viilukas, Taavi; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund; Baranov, Samary (2011). Automated Test Bench Generation for High-Level Synthesis flow ABELITE. Proceedings of IEEE East-West Design & Test Symposium 2011 (1−6).. Sevastopol, Ukraine: IEEE Computer Society.
3.1.
2011
Raik, J; Rannaste, A; Jenihhin, M; Viilukas, T; Fujiwara, H; Ubar, R (2011). Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. Proceedings of IEEE European Test Symposium, (1−6).. IEEE Computer Society Press.
3.1.
2010
Viilukas, Taavi; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund; Krivenko, Anna (2010). Constraint-based Test Pattern Generation at the Register-Transfer Level. Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 14–16, 2010 Vienna, Austria. IEEE, 352−357.10.1109/DDECS.2010.5491752.
1.1.
2008
Raik, J.; Ubar, R.; Viilukas, T.; Jenihhin, M. (2008). Mixed hierarchical-functional fault models for targeting sequential cores. Journal of Systems Architecture, 54, 465−477.
3.1.
2008
Chepurov, Anton; Di Guglielmo, Giuseppe; Fummi, Franco; Pravadelli, Graziano; Raik, Jaan; Ubar, Raimund; Viilukas, Taavi (2008). Automatic Generation of EFSMs and HLDDs for Functional ATPG. In: 11th Biennial Baltic Electronics Conference (143−146). . IEEE.
3.1.
2006
Raik, Jaan; Ubar, Raimund; Viilukas, Taavi (2006). High-Level Decision Diagram based Fault Models for Targeting FSMs. Proceedings of the 9th IEEE Euromicro Conference on Digital Systems Design: DSD2006, Cavtat, Aug. 31- Sept. 2, 2006. IEEE Computer Society Press, 353−358.
25.11.2020