An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architectures

Ubar, R.; Jenihhin, M.; Jervan, G.; Peng, Z. (2004). An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architectures. System-on-Chip Conference, 2004, Båstad, Sweden, April 13-14. SOCWARE,.
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Ubar, R.; Jenihhin, M.; Jervan, G.; Peng, Z.
System-on-Chip Conference, 2004, Båstad, Sweden, April 13-14
SOCWARE
2004
Ilmunud
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