Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation

"Leveugle, R.;Ubar, Raimund-Johannes" (1998). Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation. Proceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 1998. TU Lodz, 353−358.
publitseeritud konverentsiettekanne
"Leveugle, R.;Ubar, Raimund-Johannes"
Proceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 1998
TU Lodz
1998
353358
Ilmunud
3.2. Artiklid/peatükid lisas mitte loetletud kirjastuste välja antud kogumikes

Viited terviktekstile

Seotud asutused

Lisainfo