A Hybrid BIST Architecture and its Optimization for SoC Testing

Jervan, Gert; Peng, Zebo; Ubar, Raimund; Kruus, Helena (2002). A Hybrid BIST Architecture and its Optimization for SoC Testing. Proceedings of the IEEE 3rd International Symposium on Quality Electronic Design: IEEE 2002 3rd International Symposium on Quality Electronic Design (ISQED'02), March 18-20, 2002, San Jose, California, USA. IEEE Computer Society Press, 273−279.10.1109/ISQED.2002.996750.
publitseeritud konverentsiettekanne
Jervan, Gert; Peng, Zebo; Ubar, Raimund; Kruus, Helena
Proceedings of the IEEE 3rd International Symposium on Quality Electronic Design
IEEE 2002 3rd International Symposium on Quality Electronic Design (ISQED'02), March 18-20, 2002, San Jose, California, USA
IEEE Computer Society Press
0-7695-1562-2
2002
273279
Ilmunud
3.1. Artiklid/peatükid lisas loetletud kirjastuste välja antud kogumikes (kaasa arvatud Thomson Reuters Book Citation Index, Thomson Reuters Conference Proceedings Citation Index, Scopus refereeritud kogumikud)

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dx.doi.org/10.1109/ISQED.2002.996750

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