Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits

Ubar, R.; Brik, M. (2000). Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems: Gdynia (Poland), June 15-17, 2000. 533−538.
publitseeritud konverentsiettekanne
Ubar, R.; Brik, M.
Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems
Gdynia (Poland), June 15-17, 2000
2000
533538
Ilmunud
3.4. Artiklid/ettekanded, mis on avaldatud valdkonda 3.1. mittekuuluvates konverentsikogumikes

Viited terviktekstile

Lisainfo

INSPEC