Analysis and experimental verification of the influence of fabrication process tolerances and circuit parasitics on transient current sharing of parallel-connected SiC JFETs
Lim, J.-K.; Peftitsis, D.; Rabkowski, J.; Bakowski, M.; Nee, H.P. (2014). Analysis and experimental verification of the influence of fabrication process tolerances and circuit parasitics on transient current sharing of parallel-connected SiC JFETs. IEEE Transactions on Power Electronics, 29 (5), 2180−2191.10.1109/TPEL.2013.2281084.
ajakirjaartikkel
Lim, J.-K.; Peftitsis, D.; Rabkowski, J.; Bakowski, M.; Nee, H.P.
- Inglise
Analysis and experimental verification of the influence of fabrication process tolerances and circuit parasitics on transient current sharing of parallel-connected SiC JFETs
IEEE Transactions on Power Electronics
0885-8993
29
5
2014
2180–2191
Ilmunud
1.1. Teadusartiklid, mis on kajastatud Web of Science andmebaasides Science Citation Index Expanded, Social Sciences Citation Index, Arts & Humanities Citation Index ja/või andmebaasis Scopus (v.a. kogumikud)
WOS