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Analysis and experimental verification of the influence of fabrication process tolerances and circuit parasitics on transient current sharing of parallel-connected SiC JFETs

Lim, J.-K.; Peftitsis, D.; Rabkowski, J.; Bakowski, M.; Nee, H.P. (2014). Analysis and experimental verification of the influence of fabrication process tolerances and circuit parasitics on transient current sharing of parallel-connected SiC JFETs. IEEE Transactions on Power Electronics, 29 (5), 2180−2191. DOI: 10.1109/TPEL.2013.2281084.
artikkel ajakirjas
Lim, J.-K.; Peftitsis, D.; Rabkowski, J.; Bakowski, M.; Nee, H.P.
  • Inglise
Analysis and experimental verification of the influence of fabrication process tolerances and circuit parasitics on transient current sharing of parallel-connected SiC JFETs
IEEE Transactions on Power Electronics
0885-8993
29
5
2014
21802191
Ilmunud
1.1. Teadusartiklid, mis on kajastatud Web of Science andmebaasides Science Citation Index Expanded, Social Sciences Citation Index, Arts & Humanities Citation Index, Emerging Sources Citation Index ja/või andmebaasis Scopus (v.a. kogumikud)
Ei
WOS

Viited terviktekstile

doi.org/10.1109/TPEL.2013.2281084

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