Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment

Jervan, Gert; Ubar, Raimund; Shchenova, Tatjana; Peng, Zebo (2005). Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Proceedings of the 10th IEEE European Test Symposium: 10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005. IEEE Computer Society Press, 2−7.10.1109/ETS.2005.16.
publitseeritud konverentsiettekanne
Jervan, Gert; Ubar, Raimund; Shchenova, Tatjana; Peng, Zebo
Proceedings of the 10th IEEE European Test Symposium
10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005
IEEE Computer Society Press
0-7695-2341-2
2005
27
Ilmunud
3.1. Artiklid/peatükid lisas loetletud kirjastuste välja antud kogumikes (kaasa arvatud Thomson Reuters Book Citation Index, Thomson Reuters Conference Proceedings Citation Index, Scopus refereeritud kogumikud)

Viited terviktekstile

dx.doi.org/10.1109/ETS.2005.16