Automatic SoC Level Test Path Synthesis Based on Partial Functional Models

Tsertov, Anton; Jutman, Artur; Devadze, Sergei; Ubar, Raimund (2011). Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Proceedings of 20th Asian Test Symposium (ATS): Asian Test Symposium (ATS), New Delhi, India, 2011. New Delhi, India, 532−538.10.1109/ATS.2011.79.
publitseeritud konverentsiettekanne
Tsertov, Anton; Jutman, Artur; Devadze, Sergei; Ubar, Raimund
  • Inglise
Proceedings of 20th Asian Test Symposium (ATS)
Asian Test Symposium (ATS), New Delhi, India, 2011
New Delhi, India
1081-7735
2011
532538
Ilmunud
3.1. Artiklid/peatükid lisas loetletud kirjastuste välja antud kogumikes (kaasa arvatud Thomson Reuters Book Citation Index, Thomson Reuters Conference Proceedings Citation Index, Scopus refereeritud kogumikud)

Viited terviktekstile

dx.doi.org/10.1109/ATS.2011.79