Hybrid BIST time minimization for core-based systems with STUMPS architecture

Jervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund (2003). Hybrid BIST time minimization for core-based systems with STUMPS architecture. Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems: 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, USA, 3-5 November 2003. IEEE Computer Society Press, 225−232.
publitseeritud konverentsiettekanne
Jervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund
  • Inglise
Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, USA, 3-5 November 2003
IEEE Computer Society Press
1063-6722
0-7695-2042-1
2003
225232
Ilmunud
3.1. Artiklid/peatükid lisas loetletud kirjastuste välja antud kogumikes (kaasa arvatud Thomson Reuters Book Citation Index, Thomson Reuters Conference Proceedings Citation Index, Scopus refereeritud kogumikud)

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