A Hybrid BIST Energy Minimization Technique for System-on-Chip Testing

Jervan, G.; Peng, Z.; Ubar, R.; Shchenova, T. (2006). A Hybrid BIST Energy Minimization Technique for System-on-Chip Testing. IEE Proceedings - Computers and Digital Techniques, 153 (4), 208−216.10.1049/ip-cdt:20050064.
ajakirjaartikkel
Jervan, G.; Peng, Z.; Ubar, R.; Shchenova, T.
  • Inglise
IEE Proceedings - Computers and Digital Techniques
1350-2387
153
4
2006
208216
Ilmunud
1.1. Teadusartiklid, mis on kajastatud Web of Science andmebaasides Science Citation Index Expanded, Social Sciences Citation Index, Arts & Humanities Citation Index ja/või andmebaasis Scopus (v.a. kogumikud)
WOS

Viited terviktekstile

dx.doi.org/10.1049/ip-cdt:20050064