Virtual Reconfigurable Scan-chains on FPGAs for Optimized Board Test

Aleksejev, Igor; Jutman, Artur; Devadze, Sergei; Shibin, Konstantin (2015). Virtual Reconfigurable Scan-chains on FPGAs for Optimized Board Test. 16th IEEE Latin-American Test Symposium (LATS), Puerto Vallarta, Mexico, March 25 - 27, 2015. Puerto Vallarta, Mexico: IEEE, 1−6.dx.doi.org/10.1109/LATW.2015.7102411.
publitseeritud konverentsiettekanne
Aleksejev, Igor; Jutman, Artur; Devadze, Sergei; Shibin, Konstantin
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16th IEEE Latin-American Test Symposium (LATS), Puerto Vallarta, Mexico, March 25 - 27, 2015
Puerto Vallarta, Mexico
IEEE
2015
16
Ilmunud
3.1. Artiklid/peatükid lisas loetletud kirjastuste välja antud kogumikes (kaasa arvatud Thomson Reuters Book Citation Index, Thomson Reuters Conference Proceedings Citation Index, Scopus refereeritud kogumikud)

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dx.doi.org/dx.doi.org/10.1109/LATW.2015.7102411